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Carlo Collodi, Les Aventures de Pinocchio. Carlo Collodi, Les Aventures de Pinocchio , traduction par Isabel Violante, chronologie, presentation, notes, dossier, bibliographie par Jean-Claude Zancarini, Paris, Flammarion, 2001, 349 p., 57 FF / 8,69 ˆ Traduit de l'italien par Laura Fournier. 1 La traduction d’un texte classique est le renouvellement d’un acte d’amour pour son auteur et pour la promesse faite par celui-ci a ses lecteurs d’hier et d’aujourd’hui. Manager Cover! Les Aventures de Pinocchio de Collodi (Carlo Lorenzini), traduites par Isabel Violante et augmentees d’une presentation et d’un ample dossier redige par Jean-Claude Zancarini, naissent de cette sensibilite. Organic Help! L’ouvrage refuse en effet tout type d’interpretation qui « recherche l’effet » et incite le lecteur a reconsiderer le texte – ce qui, dans le cas de l’ouvrage de Collodi, est concretement ce qui compte le plus. Best Dental Cover Letter! Pinocchio , d’ailleurs, comme tous les classiques, porte en lui les strates d’interpretations successives, ce qui rend impraticable un rapport desenchante du lecteur avec le texte. Evaluating Research! C’est donc de la comprehension des differentes lectures dont Pinocchio est en quelque sorte la « victime passive » que l’editeur de l’ouvrage a choisi de partir, mettant ainsi en discussion la reduction du texte a un simple « conte pedagogique ». Dental Manager! La critique a en effet l’habitude de rappeler que la « gaminerie » – c’est ainsi que l’auteur definit son ?uvre dans une lettre – est parue en feuilleton, de 1881 a 1883, dans le Giornale per easy essay vacations i bambini , « le journal pour les enfants » fonde par Ferdinando Martini puis dirige par Lorenzini lui-meme. Dental Manager Cover Letter! Ainsi on ics canada resume, a souvent donne un poids excessif a la destination premiere de l’?uvre par rapport a l’evolution de l’ecriture du texte. Dental Office Letter! Ceci a conduit a une lecture reductrice, encore augmentee par le succes deferlant de l’adaptation cinematographique de Walt Disney – dont l’examen dans le dossier est fort opportun. 2 La reedition de Pinocchio dans la collection « Dossier » de Flammarion, a cote de textes litteraires consideres comme « majeurs », de romans de formation et de classiques de la pensee, suggere au lecteur un retour sur cette ?uvre.
Ce n’est pas la, bien sur, une nouveaute, mais, aujourd’hui comme hier, l’initiative conserve un certain charme « revolutionnaire ». Evaluating Of A Research! On pense par exemple a la belle edition Einaudi, publiee en 1943 avec une breve et emouvante introduction de Cesare Zavattini. Office Manager Cover Letter! L’edition Einaudi n’etait pas destinee a l’enfance, mais invitait les lecteurs a reconsiderer les aventures de la marionnette la plus celebre au monde comme un texte classique, et un classique est ce qu’il y a de plus utile pour continuer a exercer sa pensee a chaque epoque, meme dans les periodes les plus sombres, pour reprendre l’expression de Bertolt Brecht. Minor In Creative Unc! Cette meme idee parcourt les pages de cette edition, dont le dossier se termine, sans qu’il faille voir la l’effet du hasard, par une phrase d’Italo Calvino, que l’editeur reprend a son compte : « un classique, c’est un livre qui n’a jamais fini de dire ce qu’il a a dire » (p. Dental Office Manager Cover Letter! 343). Qualities Of A! Il serait donc reducteur de definir Les Aventures de Pinocchio comme« un classique de la litterature enfantine ». Best Office Manager Cover Letter! Il s’agit au contraire, comme l’ont ecrit Carlo Fruttero et Franco Lucentini, « d’un classique de la litterature tout court ». 3 Il parait tout aussi reducteur d’aborder l’ouvrage a la seule lumiere d’une lecture sociologique et plus encore –comme le souligne Jean-Claude Zancarini en analysant certains textes d’Alberto Asor Rosa– en s’appuyant sur une vision psychologisante de Collodi. Vacations! Cette « gaminerie » a ete ecrite « pour toujours », comme c’est le cas en general pour les recits, independamment de leur destination et de leur destin. Best Cover! C’est donc dans cette direction qu’il est necessaire d’avancer, pour tenter de comprendre le texte tout en choisissant, en « adultes », parmi les multiples lectures possibles. Evaluating Of A! L’?uvre de Collodi, ecrit Jean-Claude Zancarini, ne peut etre reduite a une seule lecture. Best Manager Cover Letter! « Carlo Fruttero et Franco Lucentini », poursuit l’auteur, « nous rappellent un point qui devrait etre une evidence pour un lecteur et dont nous allons tenter de faire notre profit : “ne nous laissons pas tromper par la destination primitive de Pinocchio a l’enfance et, surtout, ne nous laissons pas convaincre par ses faux amis et ses ennemis declares, qui veulent que pour le lire ou le relire il faille une cle speciale ; deliberement ‘fraiche et ingenue’, ou au contraire (mais c’est au fond la meme chose) rare et sophistiquee, voire arrogamment ‘sociale’.
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La page finale peut stupefier le lecteur. Minor Writing Unc! Avec une habilete extraordinaire, Collodi fait, encore une fois, parler Pinocchio « a lui-meme », en son for best office manager letter, interieur, avec une satisfaction non dissimulee, comme pour signifier que la reflexion personnelle etait, au fond, le but recherche : « Pinocchio se retourna pour le regarder et, apres l’avoir bien regarde, il se dit a lui-meme, avec infiniment de satisfaction : ‘Comme j’etais ridicule quand j’etais un pantin ! Et comme je suis heureux d’etre devenu un petit garcon comme il faut !’« (p. Ics Canada Resume! 314-315). 7 Au cours du recit, l’auteur n’entend pas tant montrer au lecteur, en termes pedagogiques, la distinction nette entre ce qui est bien et ce qui est mal, selon une morale universellement acceptee, que souligner la capacite de chaque individu a atteindre un stade ou il lui est possible d’arreter de reagir exclusivement aux sollicitations exterieures sans aucune reflexion personnelle. 8 Les monologues interieurs dont est capable le pantin au cours de l’histoire murissent apres coup, apres qu’il a fait ses betises, toujours « tout seul » (« da se solo ») et souvent a haute voix : « - Bien fait pour moi !… Ah ! oui, bien fait ! j’ai voulu faire le paresseux, le vagabond… j’ai voulu suivre de mauvais compagnons, et le sort me poursuit sans cesse. Best Office! Si j’avais ete un enfant comme il faut, comme tant d’autres, si j’avais eu envie d’etudier et de travailler, si j’etais reste a la maison avec mon pauvre papa, a l’heure qu’il est je ne serais pas ici, au milieu des champs, faisant le chien de garde a la porte d’une maison de paysans. Cheap! Ah ! si je pouvais naitre une seconde fois !… Mais maintenant, il est trop tard. Manager Letter! Prenons patience !… » (p. Hero! 158-161). Best Manager Cover Letter! C’est egalement le ton des autres monologues, introduits toujours par un « si j’avais fait… », « si j’avais eu… ». Qualities Of A! L’auteur utilise aussi le monologue pour exprimer la stupeur du pantin devant la vie, comme dans le chapitre XIV, lors de la rencontre avec les « assassins ». Office Manager Letter! Dans d’autres cas, le monologue sert a souligner la naivete, comme lorsque Pinocchio imagine la multiplication de ses pieces de monnaie plantees dans le Champ des miracles, au debut du chapitre XIX.
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URL : http://laboratoireitalien.revues.org/308. ISSN electronique 2117-4970. Informations Titre : Laboratoire italien Politique et societe En bref : Revue consacree a l'etude de l'Italie passee et presente comme un lieu privilegie d'etude du politique.
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A Guide to Hindi - 10 facts about the Hindi language. Hindi got its name from the Persian word Hind , meaning 'land of the Indus River'. Persian speaking Turks who invaded Punjab and Gangetic plains in cover letter, the early 11th century named the language of the region Hindi , 'language of the land of the minor writing, Indus River'. Manager Cover Letter! Just like European languages, Hindi is written from left to essay, right. You'll find many familiar words in office, English which are either Hindi or of minor writing unc, Hindi origin. For example guru, jungle, karma, yoga, bungalow, cheetah, looting, thug and avatar. In Hindi it's common to find long words created by best letter combining several other words. Essay To Buy! For example, ????????????????? [kimkartavyavimoorh] means confused, bewildered, indecisive and ??????????? [lauhpathgamini] is best dental cover letter a word created to mean train . It means 'a thing which travels on an iron path' and is a combination of three words, 'iron', 'path' and to buy 'traveller'.
But this word is only used in a funny sense, mostly in jokes, the manager, Hindi word used for qualities of a essay train is ???????? [railgadi] , literally 'rail vehicle'. Here's a Hindi tongue twister: ????? ?????-????? ?????. [kachcha papad-pakka papad] Uncooked papadum-cooked papadum. This tongue twister is best office manager cover popular in minor in creative writing, Hindi because it's very difficult to keep repeating over best dental manager cover, and over. Jokes from the two characters Santa and Banta, are very popular in Hindi. Here are two of them: ????? 60 ???? ??? ????? ??????????? ??? ?? ?? ????? ??????. ??????? ?? 40 ????, ???? ?? ???? ?????. [Santa: Kelaa kitne mein? Falwala: 1 rupaye. Santa: 60 paise mein doge? Falwala: Itne me to essay on summer, sirf kele kaa chhilkaa milegaa.
Santa: Ye lo 40 paise, mujhe bas kelaa chahiye.] Santa: How much is a banana? Santa: Would you sell it for 60 paise? Grocer: You could only get the dental manager cover, skin of the fruit for evaluating paper that price. Best Manager Cover Letter! Santa: Take 40 paise, just give me the banana, (and keep the skin). ???????? ??, ?? ?? ??? ?? ???? ????????????, ??? ?? ???? ??? ??? ?? ??. [Santa: Patahai, bachpan mein mujhe ek bus ne dhakka maar diya tha. Banta: Baap re, tu mar gaya kibacha? Santa: Yaad nahi. main tab chaar saal ka tha.] Santa: I was hit by a bus when I was a child, you know. Banta: Oh my god, did you die or survive?
Santa: I don't remember, I was only qualities of a four then. Teacher-student jokes are also popular in best manager letter, Hindi. Here is one of them: ????? ??????? ??? ?? ??? ????. ?? ??? ??? ??. ??? ?? ????? ???? ??. Organic Homework Help! ????? ????? ???? ??? ?????? ????? ?? ??, ??? ????. [Teacher: Cricket match par lekh likho. Office! Sab likh rahe the, magar ek student baitha tha. Teacher: Kyon baithe ho? Chhatr: Likh liya. Chhatr: Barish ho gayee, match radd.] Teacher: Write an essay on a cricket match. All pupils started writing except one. Teacher: Why are you sitting? Student: I've finished the essay.
Teacher: What did you write? Student: Due to rain, no match.” Hindi is a direct descendent of the ancient Indian language Sanskrit . It has evolved in its present form through Prakrit and Apabhramsa languages. Ics Canada Resume! You should be careful with the best office manager letter, use of formal and informal words in Hindi. For example, there are two common words in Hindi for the word father : ???? [pita] is a formal word, whereas ??? [baap] is an informal one. So, if you ask your Indian friend at a party How is your father? using ???????? ??? ???? ?? [tumhara baap kaisa hai] you might cause embarrassment for essay to buy you and your friend. The appropriate use should be formal, for dental manager letter example ???????? ???? ???? ??? [tumhare pita kaise hain] . Hero Essay! Hindi has many idioms which are quite frequently used in best letter, day-to-day conversations. Here are a few examples: [kar bhala ho bhala] (literally: do good, will be good) Do good and good will come to you. [jaisa karoge waisa bharoge] (literally: what you do, you pay) You reap what you sow. Hero! Here are a few interesting Hindi proverbs: ???? ???? ???? ???? ?? ?????. [bandar kya jane adrakh ka swad]
A monkey doesn't know the best office letter, taste of ginger. Of A Research Paper! Meaning: Those who don't know, can't appreciate. [thotha chana baje ghana] A hollow lentil makes more noise. Meaning: Those who are not capable of delivering, talk more. [bahti ganga me hath dhona] To wash one’s hand in the river (Ganges) Meaning: To be an opportunist. Hindi in its present form emerged through different stages, during which it was known by other names. The earliest form of old Hindi was Apabhramsa. In 400 AD, Kalidas , a famous Indian literary playwright, wrote a romantic play in Apabhramsa called Vikramorvashiyam . The most common word for greetings in Hindi is ?????? [namaste] . It’s a formal way to say hello to anybody with a sense of respect. Literally, it means ‘I bow to you’. The word is derived from two Sanskrit words: ??? [namas] meaning bow and ?? [te] meaning to you . When greeting each other, people generally bow slightly while bringing their hands in front of the manager, chest pressing them together, touching palms and pointing fingers upwards. ?????? ??? ?? [Namaste Ram jee] , Hello Ram. ?????? ????? ?? [Namaste Shyam jee] , Hello Shyam. Evaluating Of A Paper! ?????? ????? ?? [Namaste Sharda jee] , Hello Sharda. Dental Office Cover! ?????? ?? [William jee] ?????????? ?? [Victoria jee] . 10 things to know about the Hindi language. Get started with 20 audio phrases. Learn the letters of the Hindi alphabet.
Quick Fix: Essential phrases in 36 languages. BBC news in ics canada, Hindi. English Hindi dictionary. Dental Office Manager Cover Letter! Find out more about the Devangari script. Of A Research Paper! This page is best viewed in an up-to-date web browser with style sheets (CSS) enabled.
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fpga resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in best manager letter SystemC and verified the TCP RTL implementation Designed and essay on summer, Verified ZBT SRAM and Flash interface for manager cover LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and evaluating research, Synthesised the best dental office, same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Cheap To Buy? Electrical and Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the best manager letter, same.
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Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp. White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of dental manager, data. Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and evaluating the hypothesis of a, counter state graph designs into best office manager cover letter RTL and essay on summer, structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools.
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BS Electrical Engineering, University of Utah, Salt Lake City, UT. TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU. TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year. Site Location: On-Site. Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER.
Career Level: Management Manager/Director of Staff. Date of qualities essay, Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering. TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel.
Provided upper management monthly Progress Reports and dental office manager cover letter, Weekly Departmental updates. Interacted with all required agencies, vendors, and customers to meet corporate objectives and deadlines. Extensive expertise in the Engineering Process. Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and homework help, Production Review in Transiting new Designs into office cover letter a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and the hypothesis of a, Trade Studies of various Electro-Mechanical Systems. Dental Cover? Highly Knowledgeable of of a essay, CAD Systems in best dental office manager letter generation of Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required.
Extensive hands-on experience in minor System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and Test of a variety of best dental manager, Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to evaluating of a, Store Manager. Responsible for opening and best office letter, closing. Assignment of daily retail task and scheduling of available manpower.
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Generated documentation of all Photo Processing and Printing Procedures. Adhered to minor in creative unc, EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of best dental office cover letter, PLC Interfaces using OrCAD. Performed various Test Engineering activities.
Involved in assessing and performing the overall Functional and In-Circuit Test activities in the production and ics canada resume, repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and dental office manager, associated Power Supply SMD Assembly. Performed evaluation and refinement of minor, a variety of Functional Test operations, debug analyses and recommended solutions to best office manager cover, improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for organic chemistry homework the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Office Manager Cover Letter? Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly Progress Reports and Weekly Departmental updates.
Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for ics canada resume the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory. Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the office manager cover letter, RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and cheap essay to buy, provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and cover, qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.
Supervised and directed four Electrical Designers. Participated and ics canada resume, provided Technical Engineering Support to System, Concept, Equipment, Readiness and office manager cover, Production Reviews transiting the TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of software code development, system simulation and of a hero, software performance evaluations. TRMC 80 Logic in Altera FPGAs No PWB Design Errors.
Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and dental office letter, Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and of a, weekly departmental updates. Assigned design tasks and maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to letter, provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers.
Electrical Engineer 1986-1987. Module Design Engineer responsible for evaluating the hypothesis research all components of the best letter, Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development. Redesigned the Digital Signal Processor and in creative, upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for cover Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and easy vacations, MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA.
Senior Electronic Design Engineer. Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and best dental office manager cover, Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in all phases of minor writing unc, electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Best Dental Cover Letter? Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of the hypothesis of a research, a wide range of Off-the-Shelf Multibus I Modules.
DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in best office the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU.
Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and easy, Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS.
1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of dental cover letter, computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA.
Involved in Ethernet/firewall product development for chemistry homework the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and best office cover, 24K of Dual Port SSRAM using .25-micron technology. Headed the design team in the implementation of the in creative unc, chip. VHDL was used for best dental cover the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into essay to buy an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an best office letter, Intel ARM 9 processor and an ITE PCI bridge.
In charge of engineering development of to buy, board level designs for dental office both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing. Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the essay, software department for BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999.
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Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in cheap essay debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Best Dental Manager? Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools.
Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and to buy, was simulated for cover letter various digital applications. Captured top-level video inputs simulation of minor, VMIS video million images per second TV controller chip having an best dental manager, embedded processor. Enabled signal processing for digital applications. Worked in a team for writing simulation of office cover, chip. Qualities Of A Hero? Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Office Cover? Used Configuration Management Tool for cheap to buy database version control. Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses.
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Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to best office letter, Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation).
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Modeled a MC68HC11E9 Microcontoller Unit in VHDL. The unit included microprocessor and memory components. Implemented design and verification with the help of resume, ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94.
Expertise in Cadence Simulation, Acceleration and dental manager letter, Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on easy vacations, request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and optimistic and to best manager cover letter, pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in organic homework short : Have got more than 20 months of dental, experience in minor in creative writing unc the field of VLSI. Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field.
Arsanti! Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to dental, create testcases for essay to buy QA of Avanti tools. Creating testcases to check various releases of best dental office manager cover, Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer.
Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Writing Test benches for qualities of a hero designs. Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry).
Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of office cover, Top Cell with core utilization of 75%, alongwith floorplanning of hero essay, each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). Best Dental Office Cover Letter? (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design)
Designing of in creative writing unc, Standard Cells of 0.24 technology along with DRC LVS check. Best Dental Cover Letter? (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an the hypothesis, initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. Best Dental Office Manager Letter? BenchMark For LSI logic involving Congestion driven placement with a core size of cheap essay to buy, 26,000,000 micro^2. Bench Mark for best manager Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to evaluating, meet. Office Cover? Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP) EIGHT-BIT MICRO CONTROLLER.
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DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in best manager cover letter Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED.
Time Conscious. Cheap To Buy? A go-getter. Quest for perfection in all assignments. Date of dental manager cover, Birth : 02-08-1977. Organic Chemistry? Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and manager cover, Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and organic chemistry, Synthesis tools Design verification using VERA HVL.
Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date. Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and best dental office manager letter, MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). Easy Vacations? KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of dental manager letter, HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA.
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Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices. Similarly overhead data that is sent by hero essay, Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in this FPGA. Dental Office? Analyzed system requirement specifications and qualities hero essay, developed architecture for full functionality of best, chip. Coded transmit side modules of this architecture in Verilog HDL and essay, tested functionality and performance. Dental Manager Cover? Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of in creative unc, this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT.
Contesse semiconductor Corporation. April 2000 - September 2000. Designed an best dental cover, FPGA to easy essay vacations, convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions.
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Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of best manager cover, Video output data at evaluating of a 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Best Dental? Coded the entire architecture in VHDL and did functional testing and simulations of minor in creative writing, code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999. Design of Flying Adder Digital Logic for best cover letter PLL (TFP8501) Chip.
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Used Cadence Artist and Spice for analog design. Carried out dental all process corner simulations of individual design modules and completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in cheap essay to buy the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from best office letter, PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for minor Power Management Module in dental office VHDL.
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So when timing simulation comes we load our design file and the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is organic being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to best dental manager cover letter, configure the evaluating the hypothesis, FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at office manager ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART.
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REFERENCES : Can be provided based on best dental manager letter, request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Ics Canada? Simulation: Modelsim, Quicksim from office manager cover, Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for resume debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Office Letter? Languages: C, C++, perl, Unix Internals like Shell and Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98.
Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup. Worked closely with the ASIC and ics canada resume, hardware development teams with the goal of delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Best Letter? Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments.
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Checked the timing of the design generating test vectors for evaluating of a testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Best Office Manager Cover? Synthesized the circuit using Leonardo Spectrum and targeted to minor in creative unc, Lucent's ORCA series FPGA. Dental Manager Letter? Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and ics canada resume, tested the read channel chip. Worked on three different versions of the read channel. Designed the FPGA using Visual HDL generating the RTL for the design. Best Dental Office Manager? Tested the design writing VHDL test benches for the proper operation Placed and to buy, routed the best dental manager letter, design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Qualities Of A Hero? Evaluated place and manager letter, route tools for the read channel chip.
Evaluated the the hypothesis of a, design to test the read channel chip with various FPGA place and route tools. Best Manager? Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Resume? Designed and best office manager cover, tested the organic homework help, Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Best Office? Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim.
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Design of best manager cover letter, a Simple Educational Processor using VHDL. Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of evaluating of a research paper, Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer. To work where I am given the best manager, opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance.
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Wrote test bench for verification in C Used PLI for communication with Verilog. Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000.
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FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of ics canada, Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. Dental Manager? The code was written in c inline Assembly on ics canada, Host Computer. Design, simulate, and test. Programming of SRAM DRAM.
Writing Test Benches for Verification in verilog C. Performed board simulation. Environment: C, ASIC, Test Bench for best dental office cover Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Evaluating Research Paper? Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to best office manager, 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in ics canada Turbines of thermo electric Power plant. Best Dental Manager Cover Letter? The processor controls the steam temperature. Which receives the resume, signals from Boiler sensors. If due to best dental office manager cover letter, any reason the temperature goes below specified level the to buy, alarm will be activated. It had the provision of printing the Time versus heat graph controlled by office manager, the processor 24/7.Programming of the essay to buy, RAM was done by c inline assembly.
Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip. Programmed SRAM DRAM. Wrote verification code in cover verilog C Performed the design, capture the schematics and oversee the board layout. Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an easy access to feed the User input data.
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Provides Quick Access to file Opening and Executing. Provides File Viewing facility before editing the files, giving an Easy access to best dental cover letter, Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Was a member of the team, which designed the system? Other responsibilities included coding and testing.
Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on request. Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA.
August 01 till date. Verification of in creative writing unc, PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the best office manager cover, PCI 9656 for qualities essay Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. Manager Cover? There were 2 FIFOs. Easy On Summer? One for best cover letter the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition.
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Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the best dental cover, job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes.
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Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of minor in creative, a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the office cover letter, functional models in Verilog. Verified functional models.
Verified Packet buffer read and writing. Packet buffer was read and easy vacations, written as 1024 bits at a time in best dental office manager cover letter 11 clock cycles. Easy Vacations? Verified the packet Queue (PQ) which performed queuing and dequeuing of the manager, packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. Hero? RTL replaced the NOC model. Dental? Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Ics Canada Resume? Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x.
March 98 - December 98. Design and Verification of HDLC Controller (Project Lead) Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification.
Designed the HDLC controller. Involved in portioning of the cover, design into Transmitter and Receiver. Verified the HDLC. Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to organic chemistry, VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation.
Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96. Development of Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on best dental cover, HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on qualities essay, the type of access. The tool was used in best dental office cover designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.
November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and cheap, keys were scanned. Whenever any key was pressed, the make and dental, the break key codes were sent serially in on summer vacations an 11-bit format to dental office, the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and organic chemistry, CHIP layout. VLSI Logic design - Complete design flow from RTL to dental manager, layout.
Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in in creative unc architectures of PCI OHCI. Proficient with USB. Knowledge in Unix, Perl and 'C'. Best Dental Office? Knowledge in VERILOG PLI CONCEPTS.
Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Expertise in Altera /APEX FPGA. Experience in Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices.
Renoir Tool and qualities essay, Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and best office manager cover letter, De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA.
Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution.
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It is having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Dental Cover? Then for the WAN interface we have 10/100 EMAC and qualities, also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in best office letter verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the in creative writing unc, rams. Created Testbenchs for the blocks like UART, SPI DMA.
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Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the best dental office, Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage.
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Completed Place and best dental office letter, Route of the above project which was mapped with the ics canada resume, Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India.
Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in best the verification of Open Host Controller, which controls the transaction running on USB bus. Qualities Of A Hero? It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the best cover letter, information about the device. Developed the PCI Test Bench for OHCI.
Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. Easy On Summer? It is interfaced to the PCI bus for best dental office accessing the system memory. In Creative? Designed this core using both VHDL and VERILOG. This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target.
Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function. Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from best office manager cover, USB devices to minor, main memory. PCI target responds to dental office manager cover letter, configuration transaction's and other Bus Master's initiates transaction. Implemented the chemistry homework, logic for PCI Target and best office letter, PCI Master. Tested the whole project using ModelTech simulator. Essay On Summer Vacations? Synthesized the logic using Exemplar's Leonardo tool. Max+plus II tool is used for Place and Route.
Mapped the PCI core into best dental manager letter the Altera Flex10k30 device. Mapped the USB side core into essay to buy the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in progress. Total gate count for dental cover OHCI project is organic help 33,000 gates. Project : Design and verification of best dental manager cover, Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to cheap essay to buy, capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to best dental, the computer through USB. It consists of qualities essay, video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the dental manager, camera is processed by the hearsee block.
This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core.
Duration : Nov' 97 - Dec' 97. Involved in the verification of of a hero, a USB Device Core. Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Best Office Manager Cover Letter? Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the the hypothesis paper, bit stuffer in logic works, using VHDL and Verilog.
Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an dental office letter, Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Paper? Used the best manager letter, add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA.
7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for resume physical verification, TransEDA and dental manager cover, HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS.
Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Help? Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the dental office, test vectors from the viewpoint of code coverage, and furnish suggestions to the hypothesis, the verification team as per office manager cover the findings. Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is essay on summer vacations a re-configurable processor with embedded ARC core mainly targeted at the networking applications.
Responsibilities required me to best manager letter, write tests to verify the various modules of the chip, e.g. Ics Canada Resume? fabric, road-runner bus, code generator. I also did the best dental manager letter, code coverage analysis to optimize the test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in essay automobiles for best office manager communicating between various controllers inside the vehicle. Organic Chemistry Help? The project involved converting the best dental, latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Chemistry Homework? Responsibilities required me to convert the RTL to office manager, flip-flop based design and simulate the cheap essay, design to see there are no issues with the office, conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00)
The micro-controller is to be used in automotive Industry for anti-skid braking. It is evaluating of a based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. This project involved the full Network design cycle, except for RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in best office letter DSP engines. Qualities? The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block.
Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for dental office embedded applications. The project involves the Full Chip functional Verification of the qualities of a hero essay, microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation. Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of best manager letter, vectors on the netlist generated by the Synthesis tool.
Netlist to RTL conversion was also part of the project. Redesign of help, 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. Best Manager? It also involved dynamic to organic chemistry, static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at best cover the block level as well as the full chip level.
Played major role in setting up the essay to buy, test environment for the full chip. Office? Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the qualities of a hero essay, stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst. American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's).
Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. Best Office Letter? It also involved a project in C on UNIX to easy essay on summer vacations, manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon.
It focused on advanced chip synthesis methods. 1997 B.Tech. in best dental cover Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in resume Electronics Department of best dental manager cover, IT,BHU. The process involved PCB design and C coding of device driver for the LAN card. Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China. BSEE in Electrical Engineering, WU, China.
SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and essay, SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Dental Office Manager Letter? Skilled in qualities essay board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Best Office Manager Cover? Rich experience in H/W and S/W co-design for MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and of a hero essay, related network protocols, and VLSI devices and best dental, theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in firmware programming in C/C++ under PC DOS, VxWorks and ics canada resume, QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in manager real world in order:
Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of ics canada, a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols.
Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada. May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design.
Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. Best Manager Cover? The main clock is 100MHz. Bandwidth is evaluating the hypothesis of a research 10gigabit/s. Best Manager? The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic.
Wrote ASIC specification, defined interfaces and developed chip architecture. The Hypothesis Paper? Defined and best, Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in Verilog at RTL. Ics Canada Resume? Designed core-based PCI application interface and wrote testbench for office manager cover it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores.
Synthesized with Tcl scripts , and minor, analyzed timing to fix timing issues at RTL and Gate level. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Cover Letter? Defined software interface and supported firmware designers to write ASIC driver. Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time)
OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an ATM traffic scheduler. Ics Canada? It works as part of MMC fabric chipset.
It runs in two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in best dental office letter the Xilinx's XCV1000E version. Developed and implemented the dynamical linecard, modem bandwidth allocation and easy essay on summer vacations, sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in dental manager cover 512 modem schedulers. The Hypothesis Of A Research Paper? Implemented traffic congestion control based on modem and subport backpressure signals. Wrote the dental cover letter, new version of the ASIC/FPGA design specification, verification and cheap essay, test plan. Developed chip architecture, partitioned, coded in dental office cover Verilog at RTL, fixed bugs for all functions.
Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level. Writing? Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and best office cover letter, PT timing analysis for timing debug and timing closure. Wrote test script for resume VxWorks dshell and VisionICE to best office letter, test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in ics canada resume real world in cooperation of EE and CS departments. Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09.
Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an EDIF netlist core based PCI32 backend application interface in VHDL. Office Manager Cover? Wrote model drivers, testbench in ics canada VHDL, then simulated each block and best office manager cover letter, top level. Synthesized by Synopsys's Design Compiler. In Creative? Timing debug and closure by Primetime.
Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and best cover letter, analysis using Cadence Analog Work Bench. CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by writing, Synopsys and implementation in Xilinx FPGA. Best Office Manager Letter? VHDL tutorial: Traffic light system synthesized and simulated by easy on summer vacations, Mentor Quick HDL.
Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA. Best Office Manager Letter? Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and cheap essay, PCB, PC DOS and MCU programming in C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for manager letter a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the the hypothesis research, new control algorithm. FPGA design in Xilinx F1.5, and board schematic and PCB design in best dental office manager OrCAD.
PC DOS programming and MCU 8051 firmware programming in qualities of a hero C. Digital Design Center, Wuhan, China. 1994 Sept - 1996 June. Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement.
Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for best customers.
Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from ics canada resume, host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in office cover letter C and organic chemistry homework help, debugged in labs. Dental Letter? Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.
Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and PCB design in Protel, GAL, PAL, 8051 and cheap essay to buy, firmware in C, DOS programming in C. Developing an electronic system to be used for best office manager letter teaching spoken English. Leaded a team to design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for cheap the 64 audio terminals.
Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors. Utilized a modulated Laser beam; Used 8031 MCU to dental letter, be a controller and programmed in evaluating the hypothesis research paper C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Best Manager Letter? Verification Strategies in Verilog High-Speed Circuit Design.
Primetime Training Workshop PowerPC 8260 Workshop. Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and evaluating of a research paper, circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.