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Hire the essay top 3% of ocr terminal paper freelance Ruby on Rails developers . As with any technology, there’s knowing Rails and then there’s really knowing Rails. This guide offers a sampling of questions that are key to evaluating the breadth and essay depth of a candidate’s mastery of the framework. Just as France’s Train a Grande Vitesse (TGV) (traveling at speeds of up to 320 km/h) dramatically reduces travel time for modern day rail passengers, Ruby on Rails (a.k.a. “Rails”) substantially reduces the dissertation leadership time and effort required to build powerful web applications. Essay! Tim O’Reilly (founder of O’Reilly Media) refers to Rails as breakthrough technology and Gartner Research noted in a recent study that many high-profile companies are using Rails to ocr terminal paper build agile, scalable web applications. The rate at which Rails has gained popularity is noteworthy, with estimates of over 200,000 web sites currently built with the technology. Today, many high-profile companies are using Rails to build agile, scalable web applications.
Examples include Twitter, GitHub, Yammer, Scribd, Groupon, Shopify, and Basecamp, to name but a few. Rails is a framework for in politics, web application development, written in Ruby, that also features its own routing system independent of the paper web server. The goal of essay in politics Rails is to significantly simplify the homework help proofs development of essay in politics web applications, requiring less code and time than would otherwise be required to accomplish the paper ideas same tasks. To achieve this, Rails makes certain assumptions about how things “should” be done and is then designed and structured accordingly. While imbibing this “Rails view of the world” can sometimes be a bit of a culture shock for developers strongly grounded in essay in politics, other languages and frameworks, over time most come to greatly appreciate the Rails approach and homework geometry the productivity that it engenders. From a recruiting standpoint, the explosive growth in Rails popularity is both the good and the bad news. While on the one hand it makes Rails developers easier to locate, it also makes finding the jewels among them that much more elusive. Finding true Rails experts requires a highly-effective recruiting process, as described in our post In Search of the Elite Few – Finding and Hiring the essay in politics Best Developers in the Industry. Such a process can then be augmented with questions –- such as those presented herein –- to identify the sparsely distributed candidates across the paper globe who are truly Rails experts.
The manifold benefits of finding them will likely be realized in the productivity and essay in politics results that they will be able to achieve. The extent to which Rails streamlines and simplifies the development of geometry proofs web applications can mislead neophyte developers into essay, underestimating its capabilities and oversimplifying its conceptual underpinnings. While Rails is relatively easy to use, it is anything but simplistic. As with any technology, there’s knowing Rails and ocr terminal then there’s really knowing Rails. In our search for true masters of the language, we require an interview process that can accurately quantify a candidate’s position on the Rails expertise continuum. Toward that goal, this guide offers a sampling of questions that are key to evaluating the breadth and depth of a candidate’s mastery of the language. It is important to bear in mind, though, that these sample questions are intended merely as a guide.
Not every “A” candidate worth hiring will be able to properly answer them all, nor does answering them all guarantee an “A” candidate. At the end of the essay in politics day, hiring remains as much of an art as it does a science. It is not uncommon to psychology paper encounter Ruby on Rails developers whose grasp of the fundamentals and key paradigms of Rails are either weak or somewhat confused. Questions that can help assess a developer’s grasp of the Rails foundation, including some of its more subtle nuances, are therefore an important component of the interview process. Here are some examples: Q: Explain the in politics processing flow of on employment a Rails request. At the highest level, Rails requests are served through an application server, which is essay in politics, responsible for directing an incoming request into ocr terminal paper, a Ruby process. Popular application servers that use the Rack web request interface include Phusion Passenger, Mongrel, Thin, and Unicorn.
ActiveRecord is on employment, both an Object Relational Mapping (ORM) design pattern, and Rails’ implementation of that design pattern. This means that fetching, querying, and storing your objects in in politics, the database is as much a part of the API of your objects as your custom business logic. A developer may see this as an undesired side effect, or as a welcome convention, depending on their preference and level of experience. Arel provides a query API for ActiveRecord, allowing Rails developers to perform database queries without having to hand-write SQL. Arel creates lazily-executed SQL whereby Rails waits until the last possible second to send the developmental paper SQL to the server for execution. This allows you to take an Arel query and add another SQL condition or sort to the query, right up to the point where Rails actually executes the query. Arel returns ActiveRecord objects from its queries, unless told otherwise. Q: What is the essay Convention over Configuration pattern? Provide examples of how it is applied in Rails.
Convention over Configuration (CoC) is a software design pattern by which only the unconventional aspects of an application need to be specified by a developer. When the ocr terminal default convention matches the desired behavior, the default behavior is followed without any configuration being required. The goal is to simplify software development, without sacrificing flexibility and customizability in the process. Here are some examples of essay in politics how CoC principles are applied in Rails: Model and database table naming.
Rails automatically pluralizes class names to find the respective database tables. For a class Book, for example, it will expect a database table named books. For class names composed of essays on margaret multiple words, the model class name should employ CamelCase (e.g., BookClub and book_clubs ). Primary and foreign keys. By default, Rails uses an integer column named id as the essay in politics table’s primary key. Foreign key names by default follow the on writing a thesis pattern of appending _id to the singularized tablename (e.g., item_id for a foreign key into essay in politics, the items table). Reserved words for automatic functionality. On Writing A Thesis Statement! There are also some optional column names which, if used, automatically add features and functionality to Rails database tables. created_at , for example, will automatically be set to in politics the date and essay on employment time when the record was created. Similarly, updated_at will automatically be set to the date and time whenever the in politics record was last updated. Auto-loading of class definitions. Auto-loading is the “magic” by which classes appear to be accessible from anywhere, without the need to explicitly require them. Here’s how it works: When you reference a class in your code, Rails takes the class name (with namespace) as a string, calls underscore on it, and looks for a file with that name (in all directories specified in developmental psychology paper, your config.autoload_paths ). For example, if you reference a class named FileHandling::ZipHandler , Rails will automatically search for file_handling/zip_handler.rb in your config.autoload_paths . This feature often results in novice Rails programmers thinking that they don’t need to explicitly require referenced classes and that Rails will just auto-magically find them anyway.
They then become baffled when they don’t follow this convention and essay are suddenly being told by Rails that their classes can’t be found. It is important to paper note that CoC specifies a default –- but not immutable –- convention. Accordingly, Rails does provide mechanisms for overriding these default conventions. As an example, the default database table naming scheme mentioned above can be overridden by in politics, specifying the developmental psychology ideas ActiveRecord::Base.table_name as shown here: Q: What is the “fat model, skinny controller” approach? Discuss some of essay in politics its advantages and pitfalls, as well as some alternatives. “Fat model skinny controller” is an psychology paper, MVC-based Rails design pattern.
MVC is essay, itself a software design pattern that separates a system into worksheet on writing, three separate and essay in politics distinct layers; namely, Model, View, and on employment Controller. MVC strives to in politics ensure a clean separation between each of its layers through clearly defined APIs. In a well-designed MVC system, these APIs serve as firm boundaries that help avoid implementation “tentacles” extending between MVC’s logically distinct subsystems. The “Fat model skinny controller” design pattern advocates placing as much logic as possible in the Model for (a) maximum reuse and (b) code that is easier to test. That said, a common pitfall for Rails developers is to end up with “overly bloated” models by adhering too blindly to the “fat model, skinny controller” paradigm. A Thesis Statement! The infamous User model is a prime example of this.
Since many Rails apps are about the in politics user entering data into the system, or sharing information with their friends socially, the user model will often gain more and more methods, eventually reaching the point where the user.rb model becomes bulky and unmanageable in size. A few key alternatives worth considering include: Use of other objects: Extract functionality out of models into dissertation, other objects (such as Decorators or Service objects) Hexagonal architecture for Rails: Employ a hexagonal architecture that views the application as a hexagon, each side of essay which represents some sort of essay on employment external interaction the essay application needs to have. DCI (Data Context Interaction): Instead of focusing on individual objects, focus on psychology the communication and interactions between data and essay in politics its context. Q: Describe the on margaret Rails testing philosophy. Rails built testing support in from the beginning of the essay framework, and ocr terminal it became a part of the culture. As a result, there are a plethora of tools available for testing in the Rails environment. By default, Rails 4.0+ uses the essay in politics MiniTest Ruby standard library testing framework under-the-hood. There are well defined locations in essays sanger, a Rails project for tests for each layer (model, controller, routing, view, model), as well as integration tests.
Because of the MVC foundation of Rails, often these layers (with the exception of integration tests) can be tested without reliance on the other layers. For example, we can create a database record, before the test runs, that contains the attributes we expect the test to return. Our test can focus on making sure our show post controller action retrieves the post we want it to by checking to see if it returns the object we created above as expected. Essay In Politics! If not, something went wrong or our code must have a bug. Here’s an essays sanger, example of such a test:
Integration tests (often called Feature tests) will usually drive the application as if a user is clicking buttons, using testing tools like Capybara (which can simulate user actions in a variety of essay in politics manners, including driving embedded WebKit, or using Selenium). While MiniTest is a Rails out-of-the-box standard, you’ll often see the homework RSpec gem used instead. This provides a Domain Specific Language for testing that may make it more natural to read than MiniTest. Some Rails projects use the Cucumber testing framework to describe software behavior in essay in politics, plain English sentences. This is often useful when collaborating with onsite clients, or with dedicated QA resources. In the ideal world, these non-developers can write automated integration tests without having to essay on employment see a line of Ruby code. Someone who has worked extensively with Rails can be expected to possess a great deal of in politics familiarity with its capabilities, constructs, and idiosyncrasies. These questions demonstrate ways of gauging the extent and essays on margaret depth of this expertise. Q: Explain the use of yield and essay content_for in developmental psychology paper, layouts. Provide examples. yield identifies where content from the view should be inserted.
Eager loading is the mechanism for loading the essay in politics associated records of the objects returned by Model.find using as few queries as possible. Active Record’s eager loading capability makes it possible to significantly reduce the number of queries by letting you specify in essay on employment, advance all the associations that are going to be loaded. Essay In Politics! This is done by calling the includes (or preload ) method on the Arel ( ActiveRecord::Relation ) object being built. With includes, Active Record ensures that all of the specified associations are loaded using the paper minimum possible number of queries. We could therefore rewrite the above code to essay use the includes method as follows:
This revised version of essay this code will execute just 2 queries, thanks to eager loading, as opposed to 11 queries in the original version. Q: What are “filters” in essay in politics, Rails? Describe the three types of filters, including how and why each might be used, and the order in which they are executed. Developmental Psychology! Provide examples. Filters are essentially callback methods that are run before, after, or “around” a controller action: Before filter methods are run before a controller action and therefore may halt the request cycle. A common before filter is one which requires a user to be logged in for essay, an action to be performed. After filter methods are run after a controller action and therefore cannot stop the action from being performed but do have access to the response data that is worksheet statement, about to be sent to the client. Around filter methods are “wrapped around” a controller action. They can therefore control the execution of an essay, action as well as execute code before and/or after the action is performed.
For example, in a website where changes have an approval workflow, an administrator could be able to essay preview them easily with an around filter as follows: Note that an around filter also wraps rendering. In particular, in the example above, if the view reads from the database (e.g., via a scope), it will do so within the transaction and thus present the data to preview. You can also choose not to yield and essay build the response yourself, in worksheet statement, which case the action will not be run. The order of execution is a bit tricky and is important to understand clearly. Filter methods execute in the following order:
Before filter methods, in order of definition. Around filter methods, in order of definition. After filter methods, in reverse order. Also, because of the way Ruby instantiates classes, the filter methods of a parent class’ before will be run before those of its child classes. Q: What is in politics, Rack middleware?
How does it compare to controller filters/actions? In 2007 Christian Neukirchen released Rack, a modular standard interface for serving web requests in worksheet on writing, Ruby. Essay In Politics! Rack is similar to homework geometry other similar mechanisms in other languages, such as WSGI on the Python side, or Java Servlets, or Microsoft’s Internet Server Application Programming Interface (ISAPI). Before requests are processed by your Rails action method, they go through various Rack middleware functions declared by Rails or by the developer. Rack middleware is typically used to perform functions such as request cleaning, security measures, user authorization or profiling. You can see a list of essay available middleware components (both developer defined and on writing statement those defined by Rails) by running rake middleware on the command line.
A key distinction between Rack middleware and essay in politics filters is worksheet a thesis, that Rack middleware is called before Rails does its routing and dispatching, whereas filters are invoked after this routing has occurred (i.e., when Rails is essay, about to dissertation call your controller action method). As such, its is advantageous to filter out requests to be ignored in middleware whenever possible, such as requests from in politics common attack URLs ( phpadmin.php requests, for example, can be discarded in middleware, as they will never resolve in a Rails app and is probably just some attempt to hack the site.) Q: Explain what Rails’ mass-assignment vulnerability is and Rails’ method to control field access. When the user performs a post (such as, for example, creating a new User ) Rails needs to on writing a thesis save all that new data into in politics, the database. This data is accessible from your Rails action via the params Hash. Because web apps involve updating / saving every field the user changed, Rails has some convenience methods to handle this, called mass assignment helpers. For example, prior to Rails 4, creating a new User object with parameters from geometry a submitted form looked like: params[:user] will contain keys for the elements the essay in politics user entered on the form. For example, if the form contained a name field, params[:user][:name] would contain the name entered on the form (e.g., “Jeff Smith”).
Convention vs. configuration strikes again here: name is the name of homework geometry proofs both the input element in the form and the name of the column in the database. In addition to the create method, you can update a record the in politics same way: But what happens when a hacker goes in and edits your HTML form to add new fields? They may, for example, guess that you have an is_admin field, and add it to on margaret sanger the HTML form field themselves. In Politics! Which now means that – even though you didn’t include it on the form that’s served to psychology paper ideas users – your hacker has gone in essay in politics, and made themselves an admin on dissertation on educational leadership your site! This is referred to as mass assignment vulnerability ; i.e., assigning all these fields with no filtering en masse, just trusting that the only field names and values will be those that were legitimately on the HTML form. Rails 3 and Rails 4 each have different ways of attempting to address this issue.
Rails 3 attempted to address it via attr_protected / attr_accessible controls at the model level, while Rails 4 addresses it via strong parameters and a filtering mechanism at the controller level. In Politics! Both ways allow you to restrict what keys are mapped to database columns and which columns are ignored. Ocr Terminal! Using these mechanisms, in the prior is_admin example, you can set the is_admin field to only change when code explicitly modifies the field value, or only essay, allow it to be changed in certain situations. An expert knowledge of Rails extends well beyond the technical minutia of the language. A Rails expert will have an on employment, in-depth understanding and appreciation of in politics its benefits as well as its limitations.
Accordingly, here are some sample questions that can help assess this dimension of a candidate’s expertise. Q: Why do some people say “Rails can’t scale”? Twitter was one of the on writing first extremely high profile sites to use Rails. In roughly the 2006-2008 timeframe, the growth rate of Twitter made server errors (“fail whale”) appearances a very common occurrence for users, prompting users and tech pundits to in politics lay blame at Rails’ feet. As is psychology ideas, true with any software, the causes of scalability issues can be complex and multi-faceted. Essay! Accordingly, not all of Twitter’s scaling issues can be claimed to be Rails-specific. But that said, it is important to understand where Rails has faced scalability issues and how they have been, or can be, addressed. The Ruby ecosystem has improved since Twitter’s Rails scaling problem, with better memory management techniques in dissertation on educational leadership, MRI Ruby (the core, and main, Ruby implementation) for in politics, example. Modern Rails applications typically mitigate scaling problems in essay, one or more of the in politics following ways:
Implementing caching solutions (Rails 4 introduces good advances here) Leveraging (or implementing) server or platform solutions with automatic scaling built in Profiling costly operations and moving them out of Ruby or out of one monolithic Rails app Placing some operations in a background / worker queue to be completed at a later time (e.g., perform an export operation asynchronously, notifying the user by email with a download link when the export is worksheet a thesis, completed) While there has traditionally been a one-to-one mapping between websites and Rails app (i.e., one website = one Rails app), there’s been an increasing movement towards more of a Service Oriented Architecture (SOA) approach whereby performance critical parts of the app are split off into new/separate apps which the essay in politics main app usually talks to via web service calls. There are numerous advantages to this approach. Perhaps most noteworthy is the fact that these independent services can employ alternate technologies as appropriate; this might be a lightweight / more responsive solution in Ruby, or services written in proofs, Scala (as in in politics, Twitter’s case), or Node.js, Clojure, or Go. But writing separate services isn’t the only way to speed up a Rails app. For example, Github has an on writing a thesis statement, interesting article on how it profiled Rails and ended up implementing a set of C apis for performing text escaping on the web. Q: When is Rails a good choice for a project? Rails is an essay, opinionated framework, which is either one of its most charming or frustrating attributes, depending who you ask. Rails has already made a (default, but configurable) choice about essay on employment your view templating engine, your Object Role Model (ORM), and how your routes translate to actions.
As a result of these choices, Rails is essay in politics, a great choice for a project where your application has total control over its own database, mostly returns HTML (or at on writing a thesis least doesn’t solely return JSON), and for the most part displays data back to the users consistently with the way it is stored. Because Rails is configurable, if you want to diverge from essay Rails norms you can, but this often comes at help geometry proofs an engineering cost. Want to hook into an existing MS SQL database? You can do that, but you’ll hit some bumps along the way. Want to build a single page app with Rails, returning mostly JSON object? You’ll find Rails not helping you out as much as if you had been accepting / responding with an HTML format. Q: What are some of the drawbacks of Rails?
Rails is generally meant for essay, codebases of greater than a few hundred lines of essays sanger code, and that primarily work with its own database objects. If you’re writing a web service that simply performs calculations (“give me the temperature right now in Fahrenheit”) Rails will add a lot of supporting structure “overkill” that you may not need. Additionally, Rail’s convention over configuration approach makes it sometimes not ideal for situations where you have to interact with a database schema another party controls, for example. Essay In Politics! Also, a Ruby-based solution can be a hard sell in Windows enterprise environments, as Ruby’s Windows support is not as robust as its Unix support. Like Python, the concurrency story in the default Ruby implementation (MRI; a.k.a. CRuby) is somewhat hobbled by a Global Interpreter Lock (GIL), which in homework help geometry, broad strokes means only essay in politics, one thread can execute Ruby code at essay on employment a time. (JRuby and Rubinius, other implementations of Ruby, have no GIL. A Ruby-based implementation may also not be the essay best fit for problems that want an essays on margaret, asynchronous solution (such as fetching data from multiple APIs to perform aggregate calculations, interacting with social media APIs, or responding to situations where you could get thousands of small requests a minute). Having said that, there are tools to either implement asynchronous callback based patterns in Ruby (like EventMachine), or use the Actor model of concurrency (Celluloid). And of course there are a number of background worker mechanisms if your problem fits in essay, that space.
And finally… Ruby Rookie or Gemologist? Excelling as a Rails developer requires one to be an expert in the Ruby programming language as well. Accordingly, here are some questions to help evaluate this dimension of a candidate’s expertise. Q: What are Ruby mixins, how do they work, and how would you use them? What are some advantages of using them and what are some potential problems? Give examples to support your answers. A “mixin” is the term used in Ruby for a module included in another class. When a class includes a module, it thereby “mixes in” (i.e., incorporates) all of its methods and constants. Developmental Paper! If a class includes multiple modules, it incorporates the methods and constants of all of those modules.
Thus, although Ruby does not formally support multiple inheritance, mixins provide a mechanism by which multiple inheritance can largely be achieved, or at least approximated. (A knowledgeable candidate can be expected to essay mention multiple inheritance in their discussion of Ruby mixins.) Internally, Ruby implements mixins by inserting modules into essay on employment, a class’ inheritance chain (so mixins do actually work through inheritance in Ruby). Consider this simple example: In this example, the methods of the essay in politics Student class are incorporated into DoctoralStudent class, so the paper ideas phd object supports the gpa method. It is essay, important to note that, in Ruby, the homework proofs require statement is the in politics logical equivalent of the include statement in other languages. In contrast to other languages (wherein the include statement references the contents of another file), the Ruby include statement references a named module. Therefore:
The module referenced by an include statement may either be in on writing a thesis statement, the same file (as the class that is including it) or in a different file. If in a different file, a require statement must also be used to properly incorporate the essay in politics contents of that file. Essays! A Ruby include makes a reference from the class to the included module. In Politics! As a result, if the definition of a method in the included module is proofs, modified, even at runtime, all classes that include that module will exhibit the new behavior when that method is invoked. The advantages of mixins not withstanding, they are also not without downsides and should therefore be used with care. Some potential pitfalls include: Instance variable name collisions. Different mixins may use instance variables with the same name and, if included in the same class, could create unresolvable collisions at runtime.
Silent overriding of methods. In other languages, defining something twice results in essay in politics, an error message. In Ruby, if a method is defined twice, the second definition simply (and silently!) overwrites the ocr terminal first definition. Method name clashes across multiple mixins in Ruby are therefore not simple errors, but instead can introduce elusive and essay in politics gnarly bugs. Class bloat. The ease-of-use of mixins can also lead to their “abuse”. A prime example is a class with way too many mixins that therefore has an overly large public footprint. The rules of coupling and ocr terminal paper cohesion start to in politics come into play, and you can end up with a system where changes to a module that’s frequently included can have disastrous effects. Traditional inheritance or composition is ocr terminal, much less prone to essay this type of bloat. Quite often extracting parts of a class into modules that are mixed in worksheet a thesis statement, is akin to in politics cleaning your room by putting the mess into large bins.
It looks clean until you start opening the bins. Q: Compare and contrast Symbols and Strings in Ruby? Why use one vs. the other? Symbols are singleton based on value, and immutable objects. Unlike strings, not all symbols may be garbage collected. Strings, on developmental the other hand, create multiple objects even if they share a value, are mutable, and are garbage collected when the system is done with the in politics object.
Since symbols are singleton based on value (there is only one symbol object for a value, even if it appears multiple times in developmental, a program), this makes it trivial to compare whether two symbols are the essay in politics same (Ruby basically just needs to compare their object_id values). Symbols are therefore most often used as Hash keys, with many libraries expecting options hashes with specific symbols for keys. Strings can be made immutable (“frozen”) via the freeze method. However, while this changes one behavior of a string, create two frozen strings with the developmental psychology paper same value still results in two string objects. When you use a Symbol, Ruby will check the in politics dictionary first and, if found, will use that Symbol. If the dissertation on educational leadership Symbol is not found in the dictionary, only then will the interpreter instantiate a new Symbol and put it in the heap. As stated in The Ruby Programming Language O’Reilly book (by Matz and Flanigan): A typical implementation of a Ruby interpreter maintains a symbol table in which it stores the names of all the classes, methods, and variables it knows about.
This allows such an interpreter to avoid most string comparisons: it refers to essay method names (for example) by their position in ocr terminal paper, this symbol table. This turns a relatively expensive string operation into essay in politics, a relatively cheap integer operation. Symbols are also fairly ubiquitous in Ruby (predominantly a hash keys and method names; in pre Ruby 2.1 they were also used as quasi keyword arguments, and poor man’s constants). Because of their performance, memory and usage considerations, Symbols are most often used as Hash keys, with many libraries expecting option hashes with specific symbols for keys. Symbols are never garbage collected during program execution, unlike strings (which, like any other variable, are garbage collected).
Because strings and symbols are different objects, here’s an example of paper ideas something that often catches less experienced Ruby programmers unaware. Consider the following hash, for example: You may be expecting to see 1 printed here, especially if a was defined elsewhere in your program. But, as strings and symbols are different; i.e., key (the symbol) and 'key' (the string) are not equivalent. Accordingly, Ruby correctly returns nil for a['key'] (even though this is annoying for the unsuspecting programmer wondering where her value is!) Rails has a class, HashWithIndifferentAccess , which acts like a Hash object, except it treats strings and symbols with the same values as equivalent when used as key names, thereby avoiding the above issue: There is one important caveat. Consider this controller action: This innocent looking code is actually a denial-of-service (DOS) attack vulnerability.
Since symbols can never be garbage collected (and since here we cast user input into a symbol), a user can keep feeding this endpoint with unique values and it will eventually eat up enough memory to crash the server, or at least bring it to a grinding halt. Q: Describe multiple ways to essay define an instance method in Ruby. Instance methods can of course be defined as part of a class definition. But since Ruby supports metaprogramming (which means that Ruby code can be self-modifying), Ruby programs can also add methods to help geometry existing classes at runtime. Accordingly, there are multiple techniques for defining methods in essay in politics, Ruby, as follows: (1) Within a class definition, using def (The simplest answer) This is the standard way to define instance methods of a class.
(2) Within a class definition, without using def. Since define_method is dissertation on educational, executed when Ruby instantiates the MyObject class object, you can do any kind of in politics dynamic code running here. For example, here’s some code that only creates our method if it’s being run on a Monday: Executing MyObject.new.my_method on any other day of the essays on margaret sanger week will give us an exception about essay in politics no such method existing. Sanger! Which is true: it’ll only exist on Mondays! (It’s important to note that classes are objects too in Ruby, so our MyObject class is an instantiation of a Class object, just like in a = MyObject.new , a is an instance of essay MyObject .) (3) Extending an existing class definition. Ruby also allows class definitions to be extended.
For example: The above code will result in psychology, the MyObject class having both the essay in politics say_hello and the say_goodbye methods defined. Note that this technique can also be used to extend standard Ruby classes or those defined in other Ruby libraries we are using. For example, here we add a squawk method to on margaret the standard Ruby string class: class_eval dynamically evaluates the specified string or block of essay code and can therefore be used to add methods to a class. For example, we can define the class MyObject : … and then come back at leadership a later time and essay in politics run some code to dynamically add my_method to the MyObject class: Ruby also provides a hook to check for essays sanger, undefined methods. This can be used to in politics dynamically add a method if it has not already been defined.
For example: Ruby on Rails is a powerful framework for rapid development of web applications. While all developers can benefit from its ease-of-use and flexibility, as with any technology, those who have truly mastered it will realize the on employment greatest potential and essay in politics productivity in its use. While no brief guide such as this can entirely cover the essay on employment breadth and depth of technical topics to cover in a Rails interview, the in politics questions provided herein offer an effective basis for on writing a thesis, identifying those who possess a sound and principled foundation in the Rails framework and its paradigms. My team is going to personally help you find the best candidate to join your team.
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Your Ultimate APA Format Guide Generator. APA stands for the American Psychological Association, which is an organization that focuses on psychology. They are responsible for creating APA Style. APA Style, or APA citing, is used by many scholars and researchers in in politics, the behavior and social sciences, not just psychology. APA Style is a way to dissertation, format citations.
There are other citation formats such as MLA and Chicago, but APA is most popular in the science fields. Following the same standard format for citations allows readers to in politics, understand the geometry proofs types of sources used in a project and also understand their components. The Publication Manual of the American Psychological Association is essay, currently in its 6th edition. It outlines proper ways to organize and structure a research paper, explains grammar guidelines, and homework help proofs, also how to properly cite sources. Essay? This page focuses on essay on employment, how to create APA citations. We cite sources for many reasons. Essay In Politics? One reason is to give credit to the creator of the paper work that you used to help you with your research. When you use another person’s research or information to help you with your project, it is important to give acknowledgement to that individual. This is one way to essay, prevent plagiarism. Another reason why we create citations is to provide a standard way for others to understand and possibly explore the sources we used.
To learn more about citations, check out this page on crediting work. Click here to learn more on how to be careful of plagiarism. There are two types of citations in APA. In-text citations are found in essay, the body of the project and are used when adding a direct quote or paraphrase into your work. Essay? Reference citations are found in the reference list, which is at the end of the assignment and ocr terminal, includes the full APA citations of all sources used in a project. Depending on the types of sources that you used for your project, the format you use for your citations is in politics, different for homework help each source type. There is a certain format for books, a different one for journal articles, a different one for websites, and so on. Scroll down to find the appropriate APA citation format for your sources. Even though the structure varies across different sources, see below for a full explanation of APA in-text citations and reference citations.
To learn more about APA style format, including APA’s blog, formatting questions, APA referencing explanations, click on this link for essay further reading on the style. When using a direct quote or paraphrasing information from a source, include an in-text citation in the body of your project, immediately following it. APA In-text citations may look something like this: “Direct quote” or paraphrase (Author’s name, Year, page number). See the section below titled, In-Text or Parenthetical Citations, for a full explanation and worksheet, APA format instructions.
Each source used to help with the gathering of research or information for your project is listed as a full citation in in politics, the reference list, which is usually the last part of a project. The APA citation format for each source is based on the type of source used. Scroll down to see examples of some common source formats. Most citations include the following pieces of information, commonly in this order: Author’s Last name, First Initial. (Date published). Title of Source. Location of Publisher: Publisher.
Retrieved from ocr terminal paper, URL. To determine the exact format for your full APA citations, scroll down to the section titled, “Common ALA Examples.” If you’re looking for an easy way to create your citations, use BibMe’s APA citation machine. Our APA citation maker automatically formats your citations quickly and easily. Authors are displayed in reverse order: Last name, First initial, Middle initial, followed with a period. In an APA citation, include all authors shown on a source. If using BibMe’s APA reference generator, click “Add another contributor” to add additional author names. Our free APA citation creator will format the authors in the order in which you add them. If your APA reference list has multiple authors with the same last name and initials, include their first name in brackets. Brooks, G. [Geraldine]. Essay? (2005). March . Brooks, G. [Gwendolyn]. (1949).
Annie Allen . When no author is listed, exclude the author information and start the citation with the title. When citing an entire edited book, place the names of editors in the author position and follow it with Ed. or Eds. in parentheses. See below for examples of homework geometry, citing edited books in their entirety and also chapters in edited books. How to in politics, Structure Publication Dates in worksheet on writing a thesis, APA: Place the date that the essay source was published in parentheses after the name of the author. For periodicals, include the month and day as well. If no date is available, place n.d. in parentheses.
How to Structure the Title in APA: For book titles: Only capitalize the first letter of the homework geometry first word in the title and the same for the subtitle in essay in politics, your APA citation. Capitalize the first letter for any proper nouns as well. Place this information in italics. End it with a period. Example: Gone with the wind.
For articles and chapter titles: Only capitalize the first letter of the first word in the title and on employment, the same for the subtitle. Capitalize the first letter for essay any proper nouns as well. Do not italicize the title or place it in quotation marks. Ocr Terminal Paper? End it with a period. Example: The correlation between school libraries and essay in politics, test scores: A complete overview. For magazine, journal, and newspaper titles: Write the title in on writing a thesis statement, standard form, with each important word starting with a capital letter. The Boston Globe. If you believe that it will help the reader to understand the essay type of source, such as a brochure, lecture notes, or an audio podcast, place a description directly after the title. Only capitalize the first letter. New World Punx. (2014, February 15). Statement? A state of trance 650 [Audio file].
Retrieved from https://soundcloud.com/newworldpunx/asot650utrecht. How to Structure Publication Information in in politics, APA: For books and on writing, sources that are not periodicals: Give the city and state (or city and country if outside of the U.S.) for in politics the place of publication. Abbreviate the state name using the two-letter abbreviation. Place a colon after the worksheet statement location. For journals, magazines, newspapers, and other periodicals: In APA format, place the volume number after the title. Italicize this information. Place the issue number in parentheses and do not italicize it. Afterwards, include page numbers. Journal of Education for Library and Information Science, 57 (1), 79-82. If you’re citing a newspaper article, include p. or pp. In Politics? before the page numbers.
How to Structure the proofs Publisher in APA: In APA format, the names of publishers are not necessary to include for newspapers, magazines, journals, and essay in politics, other periodicals. For books and other sources: It is not necessary to type out the name of the publisher exactly as it is geometry, shown on essay, the source. Use a brief, but understandable form of the publisher’s name. Exclude the terms publishers, company, and incorporated. Include Books and Press if it is part of the publisher’s name. End this information with a period. Little Brown and Company would be placed in the APA citation as Little Brown.
Oxford University Press would be placed in the citation as Oxford University Press. For sources found online, after the publication information, add a period. Then, add: Retrieved from URL. Do not place a period after the URL. If you’re citing a periodical article found online, there might be a DOI number attached to it. Ocr Terminal? This stands for Direct Object Identifier. If your article does indeed have a DOI number, use this instead of the URL as the DOI number is static and never changes. Essay In Politics? If the source you’re citing has a DOI number, after the on margaret sanger publication information add a period and in politics, then doi:xxxxxxx The x’s indicate where you should put the DOI number. Do not place a period after the DOI number.
If you’re using BibMe’s automatic APA reference generator, you will see an area to type in the DOI number. Lobo, F. (2017, February 23). Sony just launched the essays on margaret world’s fastest SD card. Mashable . Retrieved from http://mashable.com/2017/02/23/sony-sf-g-fastest-sd-card/?utm_cid=mash-prod-nav-sub-st#ErZKV8blqOqO. Chadwell, F.A., Fisher, D.M. (2016 April-June).
Creating open textbooks: A unique partnership between Oregon State University libraries and press and open Oregon State. Open Praxis, 8 (2), 123-130. doi:EJ1103945. APA Citations Format and Examples: Author’s Last name, F. M. (Year published). Essay In Politics? Title of book . Saenz, B.A. (2012). Aristotle and Dante discover the secrets of the universe . Looking for an APA formatter? Don’t forget that BibMe’s APA citation generator creates your citation quickly and easily. Citations for developmental paper E-Books found online:
Author’s Last name, F.M. (Year published). Title of essay in politics, book . Retrieved from URL. Colwin, L. (2014). Happy all the time. . Retrieved from https://books.google.com/books?id=EemmBAAAQBAJlpg=PP1dq=happypg=PP1#v=onepageq=happyf=false. Notice that for e-books, publication information is excluded from the dissertation leadership citation. Citations for essay Chapters in Edited Books: Chapter author’s last name, F.M. (Year published). Title of chapter.
In F.M. Last name of Editor (Ed.), Title of book (p. x or pp. x-x). Location: Publisher. doi:xxxxxxx. Longacre, W.A., Ayres, J.E. (1968). Archeological lessons from an Apache wickiup. In S.R. Binford L.R. Binford (Eds.), Archeology in cultural systems (pp. Developmental Psychology Ideas? 151-160).
Retrieved from https://books.google.com/books?id=vROM3JrrRa0C=PP1=archeology=PR9#v=onepage=archeology=false. Editor, A.A. (Ed.). (Year published). Title of edited book . Location: Publisher. Gupta, R. (Ed.). (2003). In Politics? Remote sensing geology . Germany: Springer-Verlag. Author’s Last name, F.M. (Year published). Title of article or page . Retrieved from URL.
Mardell, M. (2017). Facing the robotic revolution . Retrieved from on educational leadership, http://www.bbc.com/news/technology-39028030. Looking for an APA formatter to cite your website sources? Use BibMe’s APA citation generator! Citations for Journal Articles found Online: Author’s Last name, F.M. (Date published).
Title of essay in politics, article. Title of journal, volume number (issue number), page range. doi:xxxxxx. Spreer, P., Rauschnabel, P.A. (2016, September). Worksheet On Writing A Thesis Statement? Selling with technology: Understanding the essay in politics resistance to essays on margaret sanger, mobile sales assistant use in in politics, retailing. Journal of essay, Personal Selling Sales Management, 36 (3), 240-263. doi:10.1080/08853134.2016.1208100. Don’t forget, BibMe’s APA formatter, or APA citation generator, helps your cite your sources quickly and easily! Our free APA citation maker is simple to use! Citations for Newspapers found Online: Author’s Last name, F.M. (Year, Month Day).
Title of article. Title of Newspaper . Essay In Politics? Retrieved from URL. Khullar, D. (2017, February 22). Bad hospital design is making us sicker. The New York Times . Retrieved from https://nyti.ms/2lujQ76. Looking for an APA formatter to help you cite your newspaper sources? Check out BibMe’s APA citation machine! Our APA format generator, or APA citation builder, creates your citations quickly and easily. In Text and Parenthetical Citations. What is an APA In Text Citation or Parenthetical Citation? The purpose of APA in text and on employment, parenthetical citations is to give the in politics reader a brief idea as to where you found your information, while they’re in the middle of reading or viewing your project.
You may include direct quotes in the body of your project, which are word-for-word quotes from another source. Dissertation On Educational Leadership? Or, you may include a piece of information that you paraphrased into your own words. These are called parenthetical citations. Essay In Politics? Both direct quotes and worksheet on writing a thesis statement, paraphrased information include an in text citation directly following it. You also need to include the full citation for the source in the APA reference list, which is usually the last item in a project. In Text Citations for Direct Quotes:
In APA format, the in text citation is found immediately following the direct quote. Essay? It should include the page number or section information to help the reader locate the quote themselves. Buck needed to adjust rather quickly upon his arrival in Canada. He states, “no lazy, sun-kissed life was this, with nothing to do but loaf and on writing statement, be bored. Essay In Politics? Here was neither peace, nor rest, nor a moment’s safety” (London, 1903, p. 25). In Text Citations for paper Paraphrased Information: When taking an idea from another source and placing it in essay in politics, your own words, it is not necessary to include the page number, but you can add it if the source is large and you want to direct readers right to the information.
At the paper ideas time, papyrus was used to create paper, but it was only grown and available in mass quantities in Egypt. This posed a problem for the Greeks and in politics, Romans, but they managed to have it exported to their civilizations. Papyrus thus remained the material of choice for paper creation (Casson, 2001). How to Format In Text and Parenthetical Citations: After a direct quote or paraphrase, place in parentheses the last name of the author, add a comma, and psychology paper, then the year the source was published. If citing a direct quote, also include the essay page number that the ocr terminal information was found on. In Politics? Close the parentheses and add a period afterwards. In APA format, if the author’s name is included in the text of your project, omit their name from the dissertation on educational in-text citation and only include the other identifying pieces of information. Smith states that, “the Museum Effect is concerned with how individuals look at a work of art, but only in the context of looking at that work along with a number of other works” (2014, p. 82). If your source has two authors, always include both names in each in-text citation. If your source has three, four, or five authors, include all names in the first in-text citation along with the date.
In the following in text citations, only include the first author’s name and follow it with et al. 1st in-text citation: (Gilley, Johnson, Witchell, 2015) 2nd and any other subsequent citations: (Gilley, et al.) If your source has six or more authors, only include the in politics first author’s name in the first citation and follow it with et al. Include the year the source was published and the page numbers (if it is a direct quote). 1st in-text citation: (Jasper, et al., 2017) 2nd and any other subsequent citations: (Jasper, et al., 2017) If your source was written by a company, organization, government agency, or other type of group, include the group’s name in full in the first in text citation. In any in text citations following it, it is acceptable to shorten the group name to something that is simple and understandable. 1st citation: (American Eagle Outfitters, 2017) 2nd and subsequent citations: (American Eagle, 2017)
Check out this page to ocr terminal, learn more about parenthetical citations. Also, BibMe’s APA citation machine creates your parenthetical citations quickly and easily. Towards the end of creating a full reference citation, you’ll see the option to create a parenthetical citation in the APA format generator. The listing of all sources used in your project are found in the APA reference list, which is usually the last page or part of a project. Included in this reference list are sources you used to gather research and other information. In APA format, it is not necessary to include personal communications in the reference list, such as personal emails or letters. These specific sources only need in-text citations, which are found in the body of your project. All APA citations, or references, are listed in in politics, alphabetical order by the author’s last name. If you have two sources by the same author, place them in order by the year of publication.
Thompson, H.S. Leadership? (1971). Fear and essay, loathing in Las Vegas: A savage journey to the heart of the American dream . Thompson, H.S. (1998). The rum diary . If there are multiple sources with the same author AND same publication date, place them in homework, alphabetical order by in politics the title. Dr. Suess. (1958). The cat in the hat comes back.
New York, NY: Random House. Dr. Suess. (1958). Yertle the turtle. New York, NY: Random House. In an APA citation, if a source does not have an author, place the on educational source in alphabetical order by the first main word of the title. Need help creating the citations in your APA reference list? BibMe’s APA formatter can help!
Our APA citation machine creates your citations by entering a keyword, URL, title, or other identifying information. Need to create APA format papers? Follow these guidelines to produce a research paper in APA format: In an APA style paper, the font used throughout your document should be in Times New Roman, 12 point font size. The entire document should be double spaced, even between titles and headings. Margins should be 1 inch around the entire document and indent every new paragraph using the tab button on in politics, your keyboard. Place the pages in the following order: Title page (An APA format title page should include a title, running head, author line, institution line, and author’s note). (Page 1) Abstract page (page 2) Text or body of research paper (start on page 3) Reference List Page for tables (if necessary) Page for figures (if necessary) Appendices page (if necessary) The title page counts as page 1. Number the pages afterwards using Arabic numbers (1, 2, 3, 4…). What is a running head? In an APA paper, next to on margaret, the page numbers, include what is called a “running head.” The running head is a simplified version of the essay title of ocr terminal, your paper.
Place the essay running head in the top left corner of your project and place it in capital letters. On the title page only, include the phrase: Running head. Title page example: Running head: QUALITY LIBRARY PROGRAMS. For the rest of the paper or project, do not use the term, Running head. Example of homework help, subsequent pages: QUALITY LIBRARY PROGRAMS.
Microsoft Word, Google Docs, and many other word processing programs allow you to essay in politics, set up page numbers and a repeated running head. Use these tools to make this addition easier for you! If you’re looking for an APA sample paper, check out the other resources found on BibMe. Using BibMe to Create Citations for your Reference List or Bibliography. Looking to cite your sources quickly and easily? BibMe’s APA formatter, or APA citation generator, helps you generate your APA citations by entering a title, ISBN, URL, or other identifying information. Background Information and History of ocr terminal paper, APA: The American Psychological Association was founded in 1892 at in politics Clark University, in Worcester, Massachusetts.
APA style format was developed in 1929 by scholars from a number of different scientific fields and backgrounds. Their overall goal was to develop a standard way to document scientific writing and research. Since its inception, the APA Style Manual has been updated numerous times and it is now in ocr terminal paper, its 6th edition. The 6th edition was released in 2010. In 2012, APA published an addition to their 6th edition manual, which was a guide for essay in politics creating APA citations for electronic resources. Today, there are close to essay on employment, 118,000 APA members. There is an essay annual convention, numerous databases, and journal publications. Some of on educational leadership, their more popular resources include the database, PsycINFO, and the publications, Journal of Applied Psychology and Health Psychology. Our citation guides provide detailed information about all types of sources in MLA, APA, Chicago and Turabian styles. If required by in politics your instructor, you can add annotations to your citations.
Just select Add Annotation while finalizing your citation. You can always edit a citation as well. Remember to evaluate your sources for leadership accuracy and in politics, credibility. Questionable sources could result in a poor grade!
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What Is Politics?: Essays on Politics
7 Things Every ESL Teacher Should Teach Students About Essay Writing. “Every good story has a beginning, a middle and an end.” Many of us recall our teachers drilling this writer#8217;s mantra into us and our fellow students. In Politics? This is dissertation on educational as true for a good essay as it is for a good story. An essay needs a coherent structure to essay, successfully articulate its arguments, and strong preparation and planning is worksheet a thesis crucial to providing that structure. In Politics? So, how do we go about this? After all, essay writing can be challenging for the ESL student. Not only does the student writer have to contend with the challenges of ordering their thoughts and constructing their arguments, they have to do this in their second language. Navigating the on employment rocky bluffs of syntax and idiomatic expressions isn#8217;t easy at in politics the best of times! So, here are some helpful hints that will allow your students to weave together a coherent and persuasive essay with less stress. The 7 Helpful Habits of ESL Essay Writing. 1. Build the essay around a central question. Encourage your students to build all their writing around one central question of the essay.
That central question is the engine of the writing, it should drive everything! If a word or sentence is not assisting that forward motion toward the paper explication of that question and essay in politics, its possible answers, then it needs to be reworded, rephrased or just plain cut out and discarded. Lean writing is merciless. Focusing on that central question throughout the prewriting, writing and rewriting stages helps develop the critical faculties required to discern what to homework help, keep and what to throw away. 2. Use the traditional 5-paragraph essay structure. Providing a clear structure for the student to approach essay writing can do much to build their confidence. The 5-paragraph essay, or #8220;hamburger#8221; essay, provides that clear structure for emergent ESL writers.
Generally, this structure employs five separate paragraphs for the entire essay. Essay In Politics? Each paragraph serves a specific purpose, melding together to form a coherent whole. Paragraph 1: The introductory paragraph. It makes the thesis statement, orientating the psychology paper reader to the purpose of the essay. Paragraphs 2 to 4: The body paragraphs. These make individual points that are further backed up by the various forms of evidence. Paragraph 5: The conclusion paragraph. This provides a summation of the arguments and essay, a final statement of the thesis. Worksheet A Thesis? While they do not need to follow it rigidly forever, this simple structure outlined above can serve as excellent training wheels for your students.
Using the 5-paragraph structure as outlined above makes planning clear cut. Once they have their theses and are planning their paragraphs, share with the students the ridiculously useful acronym P.E.E. This stands for point, explanation, evidence. Each body paragraph should make a point, or argument, in favor of the central thesis, followed by an explanation of this point and essay in politics, relevant evidence to back it up. Homework Geometry? Extol the necessity for essay in politics students to constantly refer to their planning. Help? The mind-mapping techniques popularized by Tony Buzan can be useful at the planning stage and make for essay easy reference points to ensure focus is maintained throughout the essay. On Employment? Having a visual reference such as this can help ensure that your student-writers see each piece of the whole as well as that elusive #8220;bigger picture,#8221; so it become a case of seeing the forest and the trees! Just as the planning is crucial, so too is the research. Often ideas or connections do not occur until the writing process has begun. This is a good thing.
Essay writing is a creative act, so they can have more ideas along the way and work them in. The key is to always be able to back up these ideas. Students who have done their homework on their subject will be much more confident and articulate in expressing their arguments. Even with thorough planning and in politics, research, writing oneself into a linguistic cul-de-sac is worksheet on writing a thesis a common error. Once the plan is completed and the student embarks on the choppy seas of in politics, essay writing, it may or may not be plain sailing. Developmental Psychology Paper Ideas? Often, especially with our higher level students, unforeseen currents can pull the student-writer off course.
Sometimes just abandoning the sentence helps. Going back to the drawing board and rewriting it is often best. Essay? Students can be creative with their sentence structures when expressing the simpler ideas and arguments. However, when it comes to expressing the more complex concepts, help them learn to use shorter sentences to help, break down their arguments into smaller, more digestible chunks. Essay? Essay writing falls firmly in the camp of non-fiction. That is a given. However, that does not mean that some of the techniques more traditionally associated with fiction, poetry and drama cannot be used.
One technique that is particularly useful in essay writing is repetition. Just as poetry relies heavily on rhythm, so too does argument. Repetition can provide that sense of rhythm. Written language has its origins in the oral language. Psychology Paper Ideas? Think of the great orators and demagogues and their use of repetition. Speech-writers are well aware of the power of repetition. The writing principle of the #8220;rule of 3#8221; states that ideas expressed in these terms are more convincing and memorable.
This is true of words and the ideas they are expressing. Essay In Politics? The very structure of the 5-paragraph essay lends itself to planning for homework this repetition. Each idea that is explored in a body paragraph should be outlined first in the introductory paragraph. The single body paragraph devoted to the idea will explore it at in politics greater length, supported by evidence. The third rap of the hammer occurs in the summation of the dissertation on educational leadership concluding paragraph, driving the point securely and convincingly home. As mentioned at the start of this post, every good essay has a beginning, middle and an end.
Each point made, explained and in politics, supported by evidence is a step toward what the writing teacher Roy Peter Clark calls closing the circle of meaning. On Margaret Sanger? In planning for the conclusion of the essay, the students should take the opportunity to reaffirm their position. Essay? By making reference to the points outlined in developmental psychology paper ideas the introduction, driving them home one last time, the student-writer is bringing the essay to a satisfying full circle. This may be accomplished by essay employing various strategies: an apt quotation, referring to future consequences or attempting to inspire and mobilize the reader. Ending with a succinct quotation has the double benefit of lending some authoritative weight to on employment, the argument while also allowing the student to select a well-written, distilled expression of their central thesis.
This can make for a strong ending, particularly for ESL students. Often the essay thesis will suggest its own ending. If the essay is structured around a problem, it is frequently appropriate to end the essay by offering solutions to that problem and essay, outlining potential consequences if those solutions are not followed. In the more polemical type essay, the student may end with a call to arms, a plea for action on the part of the reader. The strategy chosen by the student will depend largely on what fits the central thesis of essays, their essay best. For the ESL student, the final edit is essay in politics very important. It is one final chance to check form and meaning.
For all writers this process can be daunting, but for language students especially. Often ESL students will use the same words over and over again due to a limited vocabulary, encourage your students to on margaret, employ a thesaurus in in politics the final drafting before submission. Paper? This will freshen up their work, making it more readable. This will also increase their active vocabulary in the long run! Another useful strategy to use at this stage of the process is to encourage students to read their work aloud before handing it in. Essay In Politics? This can be good pronunciation practice, and allows for an opportunity to listen for grammatical errors. It also helps the students to hear where punctuation is required in the text, helping the overall rhythm and readability of the writing. Essays are a great way not only for students to learn how the language works, but also to learn about essay on employment themselves.
Formulating thoughts and arguments about various subjects is good exercise for not only the students#8217; linguistic faculties, but also for understanding who they are and essay in politics, how they see the world. If you liked this post, something tells me that you'll love FluentU, the dissertation on educational leadership best way to teach English with real-world videos. FluentU brings language learning to life with real-world videos. Learning a foreign language becomes fun and easy when you learn with movie trailers, music videos, news and in politics, inspiring talks. FluentU is homework help proofs a participant in the Amazon Services LLC Associates Program, an affiliate advertising program designed to provide a means for sites to in politics, earn advertising fees by advertising and linking to Amazon.com.
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Short essay on Politics and Politicians
fpga sample resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in in politics, ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in worksheet on writing a thesis statement, SystemC and verified the TCP RTL implementation Designed and Verified ZBT SRAM and Flash interface for essay, LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in essay, the development of in politics a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and dissertation on educational, Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of essay TCP/IP Stack. A detailed test plan was created and SystemC models of the functional blocks were written to test the paper whole of TCP/IP Implementation. Designed and essay in politics, verified the LEXRA RISC Processor Interface with the essay on employment functional blocks and verified the same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.
Integrated all functional RTL modules and in politics, created a system level top. Perl scripts where written to manage the worksheet a thesis statement files and test cases. Created the Vera testbench environment for the whole chip. Modified the SPI-4 soft core both on the Sink and Source data paths. Essay! Synthesized the modified RTL code on Synplifypro and implement the leadership netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the RTL and essay, post layout netlist for essay on employment, functionality and timing. Ingress FPGA for essay, line card: Designed and implemented the Network Processor interface on ocr terminal the Ingress traffic flow towards the Switch fabric. The module also implements policing, segmentation, Packet format modifications and sends the packets across to in politics, the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the developmental ideas complete Ingress FPGA 1,800,000 gates.
Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the same to verify the modified RTL code and synthesized gate level netlist. The job involved understanding the Accelar simulation environment and modifying the same in accordance with the new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of essay Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Geometry! Designed testbench to test the DesignWare 8051 functionality. Essay! Mapped to essays on margaret, whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and in politics, Xilinx M1 implementation tools. On Writing A Thesis Statement! The pre-layout and essay, post-layout simulations were done on MODELSIM simulation environment.
SOC integration of statement Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Project managed the essay whole simulation work of the essay on employment USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing debugging of the functionality of the design. USB SIE Serial Interface Engine : Designed tested of all the essay modules of Serial Interface Engine. Project managed the worksheet on writing statement whole simulation work of the Serial Interface Engine. Essay! Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Responsible for testing debugging of the functionality of the SIE USBC design.
Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in paper, the kernel development of the simulator. Design and implemented an intermediate format for the simulator. Wrote extensive test cases to test the various constructs and essay, expressions of a thesis VHDL according to SPEC defined by in politics IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger. Digital Corp.
San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an a thesis statement, existing PowerPC 603 cpu simulation model to essay in politics, communicate between an ASIC and a C code simulator, including the addition of worksheet on writing a thesis decoders, latches, and state-machine modifications. In Politics! Designed VHDL logic code that enhanced the 603 cpu model by generating an essays on margaret, internal address bus busy signal when an address-only phase is initiated by essay in politics the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and debugging of the psychology paper ASIC s internal logic, including cpu and essay in politics, pci address space, SRAM, cache, BAR and other registers. Co-developed C code for ocr terminal, parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and essay, its 603 bus logic. Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp.
White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the leadership average byte value from 16 bytes of data. Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and counter state graph designs into RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools. Essay! Developed a C code program that calculates a least-sum path of distances squared for essay, a trade study that will implement ATM networking hardware on a RF communications data link. Researched and essay in politics, wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over a RF communications data link.
Amtel Corp. Boxsboro, OR. Configured and validated the compatibility of various PCI and EISA LANs and SCSI controllers and devices on quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of Utah, Salt Lake City, UT.
TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU. TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year.
Site Location: On-Site. Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Career Level: Management Manager/Director of Staff. Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering.
TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in essay, this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required agencies, vendors, and customers to meet corporate objectives and essay, deadlines.
Extensive expertise in the Engineering Process. Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and essays on margaret, Support to System, Concept, Equipment, Readiness and essay in politics, Production Review in Transiting new Designs into a Solid Product. On Margaret! Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of in politics various Electro-Mechanical Systems. On Margaret! Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs.
Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in essay in politics, System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and Test of a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager.
Responsible for opening and closing. Assignment of daily retail task and scheduling of available manpower. Providing customers with benefits of my expertise in the Art of Woodworking. Upgraded and sanger, re-merchandise entire store increasing net sales by 30 . Have sold well over essay 250,000 woodworking tools in dissertation leadership, 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. In Politics! Handing of Customer questions and accountable for cash flow. Expertise acquired in the service and maintenance of essays on margaret sanger Fuji Photo Processing Equipment. Generated documentation of in politics all Photo Processing and Printing Procedures.
Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and on margaret, performing the overall Functional and In-Circuit Test activities in the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and essay in politics, associated Power Supply SMD Assembly. Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms.
Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and worksheet on writing a thesis, a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.
Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory. Technical Integration Lead to an engineering group of essay in politics 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and developmental paper ideas, Depot Integration.
Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is essay, based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.
Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and paper ideas, Production Reviews transiting the TRMC Design into essay in politics a solid Product with the help of developmental paper Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and essay in politics, Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in a thesis, the performance of software code development, system simulation and software performance evaluations. Essay In Politics! TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into on margaret sanger developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates.
Assigned design tasks and maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and in politics, qualified to paper, MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and in politics, tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and dissertation on educational leadership, utilization of Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the in politics Module Design Process. On Employment! Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development.
Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of in politics Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for essay, Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer. Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and in politics, Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors.
Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on on writing a thesis statement a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. In Politics! Designed/Developed a Dual Port Module on ocr terminal paper a two-sided PWB using light table, which allowed the i ncorporation of essay a wide range of Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide.
Worked in essays on margaret sanger, the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in in politics, the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Ocr Terminal Paper! Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Oversaw building of essay unit and performed engineering inspections;Performed initial testing and essay on employment, qualification testing. PANAMETRICS Inc., Waltham MA.
Design Engineering Aide. Under direction of Physicist and in politics, Electrical Engineers worked as a member of the worksheet on writing a thesis statement Radiation Physics Laboratory while attending NU. Performed tasks in essay, Prototyping, Development and ocr terminal paper, Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at essay in politics Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and paper, Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS.
1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in essay in politics, SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and ocr terminal paper, SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of essay in politics a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for ocr terminal paper, the current ASIC Ethernet hub/switch. In Politics! This SOC included an a thesis, ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. Headed the essay design team in the implementation of the chip.
VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Developmental Paper! Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and in politics, an ITE PCI bridge. In charge of on writing statement engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Essay In Politics! Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing. Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the software department for BIOS and POS functionality.
MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to essay on employment, February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team. Involved in essay in politics, product planning for on writing a thesis statement, a new family of OEM image processing controllers. In Politics! These controllers are installed in high-end scanners and developmental ideas, allow Virtual Rescanning while automatically changing the essay image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of help proofs product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Essay! Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the system architecture for a second ASIC that became the psychology paper system intelligence.
This contained an embedded ARM7 processor, PCI interface, DRAM, etc. In Politics! Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in proofs, .25-micron technology. VHDL was used for essay, the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team.
Responsibilities included scheduling, budgeting and product development for both board and ocr terminal paper, system level Raid products. Involved in in politics, defining the developmental next generation architecture of Raid controllers that was comprised of essay in politics a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the homework help proofs hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital.
Designed several other Raid controller boards that were used for essay, the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in essays on margaret, implementing procedures between Document Control and Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the next generation DAT tape controller ASIC. Essay In Politics! This chip was implemented in essay on employment, .6-micron technology and has approximately 80K gates. Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of essay DRAM buffering and FLASH EEPROM.
Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the worksheet a thesis Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at essay in politics Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments.
Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of ideas software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products. A 16 and 32 bit version of in politics this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Help Geometry! Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. In Politics! Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA.
October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system. During the design phase of the on employment CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the essay in politics system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to essay on employment, October, 1984.
PROJECT MANAGER/SENIOR ENGINEER. Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the essay software and manufacturing departments efforts on the project. Developmental Ideas! Designed the essay in politics hardware and psychology paper ideas, firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of essay in politics 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of a new processor and the related I/O controllers.
Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator.
Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work.
Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date.
Development of a stand alone device to essays on margaret, measure moisture content of various agricultural products. Involved in essay in politics, Design and development of automatic moisture meter both independent and ideas, computer interfacable. Essay In Politics! First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in ocr terminal, sensor design. Design and coded same using C. Essay! Handled design and fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for developmental, the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in terms of essay in politics percentage moisture. Development of calibration technique based on homework help proofs method of least squares. Writing source code and test benches in VHDL for interfacing of 64K RAM, ROM, decoder and essay in politics, their interfacing with the A/D converter and PGA.
Simulation of on employment calibration process and verification of functionality and timing errors for essay, same. Synthesizing code on Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of geometry proofs a 8-bit micro-controller having features of in politics INTEL 8051 microcontroller. Dissertation! The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and in politics, debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools.
Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at essay 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications.
Worked in a team for simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from essay sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses.
Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to be measured for different parameters. The selection of on employment photodiodes was done to opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and essay in politics, display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051.
Further, an FPGA was developed to perform the application of microcontroller 8051 and developmental, the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.
Designed and essay in politics, developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for the instruction set of 8085 in VHDL. Wrote source code for the ALU to geometry, perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Essay In Politics! Simulation of the functionality of the on margaret sanger processor using test benches on essay in politics Active HDL simulation package in homework geometry proofs, Window NT environment. synthesized the same on XILINX FPGA.
Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer. Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of essay in politics know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for on writing a thesis statement, 8085. Department of essay science and ocr terminal paper, technology. Sept 1996- March 1997.
Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD. Checked the functionality of the essay in politics same and its interfacing with the sensor. Documentation of ocr terminal paper instrument. Involved in selection of principle of essay in politics purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry.
Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Essay On Employment! Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and essay, interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Help Geometry Proofs! Responsible for working with clients on intensive short term methodology training. Responsible for training students in VHDL, synthesis and methodology. Essay In Politics! Aid in adaptation of training materials and essay, development of new training classes. Paper publications and presentations have been made on essay Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and oil seedsin various national journals.
Training has been imparted to various engineers and on employment, students of engineering colleges from time to time. Essay In Politics! Significant contribution in organization of leadership various seminars and conferences related to essay in politics, instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for on writing a thesis, a Germany based company. Successful completion of the project lead to the sale of an emulation system.
Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences. Essay! Implemented Verification Flow. Identified introduced Cadence tools to the Verification process.
Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and developmental psychology paper, provided optimization ideas. Offered on essay site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to essays sanger, write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.
Worked closely with Quickturn RD and essay, a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to integrate all of these products. Provided post-sales technical support and developmental psychology paper, worked to in politics, increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for essay on employment, maximum performance optimizations. Essay! Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of ocr terminal paper their design, testbench and memory models to be cycle based. Debugged differences in essay, simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron.
Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to worksheet, be cycle based, and making the LogicVision environment compatible to in politics, Speedsim. Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools.
Presented demos and presentations at DAC 98 and on employment, DAC 00. Corporate Technical Support Specialist: Provided technical support for all of in politics Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. Providing workarounds to customer issues and working with RD to essay on employment, get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL.
The unit included microprocessor and memory components. Essay In Politics! Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and on employment, ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and in politics, Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER.
To achieve excellence, to be resourceful and optimistic and to geometry, pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in short : Have got more than 20 months of essay in politics experience in the field of on writing statement VLSI. Essay! Worked in logical design for essay on employment, 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!
Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for essay in politics, QA of Avanti tools. Creating testcases to check various releases of Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for dissertation on educational, various small Designs. Writing Test benches for designs.
Writing Scripts to in politics, check the designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). Essays Sanger! (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns.
The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of in politics training program in Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. On Margaret Sanger! (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an essay in politics, initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. On Educational Leadership! BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)
EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on essay in politics chip.The design incorporates all of the features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the on writing a thesis other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is essay in politics, a general purpose device but one that is meant to read data, perform limited calculation on that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the on writing a thesis statement following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b.
DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. A go-getter. Quest for perfection in all assignments.
Date of Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.
Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and essay in politics, Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). Leadership! KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Essay In Politics! Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of on writing HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for in politics, those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of on writing HUDSON device like Loss of Clock, Out of essay Frame, Bit Parity Errors (BIP) and reported them to MPC8260.
Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and dissertation, implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of essay in politics design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation.
October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Developmental Psychology Paper! Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to in politics, corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is dissertation leadership, sent to HMVIP interface in correct time slot at in politics correct frame location.
There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and essays, developed architecture for in politics, full functionality of ideas chip. Coded transmit side modules of essay this architecture in dissertation on educational, Verilog HDL and tested functionality and performance. Essay! Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Dissertation On Educational! Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.
Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and in politics, POS-PHY-3 bus on ocr terminal paper either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Essay In Politics! Used two FIFOs in ocr terminal, Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. In Politics! Generated random set of valid test cases using a seed value. Used Turbo C for psychology, writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface.
This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to essay, even support SXGA+ and W-UXGA. Developmental Psychology Paper Ideas! Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. In Politics! It also generates autogreying patterns automatically to test LCD monitor. Involved in dissertation on educational leadership, digital architecture design of chip. Essay In Politics! Coded the entire architecture in VHDL and did functional testing and simulations of code. Help! Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999.
Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to essay, 350MHz). Did coding of digital logic in VHDL. Essay On Employment! Performed synthesis of in politics design using Synopsis DC. Ocr Terminal! Used SPICE for analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection.
Rate of video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz). Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and essay, Spice for analog design. Carried out all process corner simulations of ideas individual design modules and completed closed loop simulations of PLL.
Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from in politics PC Video cards to paper ideas, LCD monitor.
Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in VHDL. Essay In Politics! Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998.
Design of Single Phase Energy Meter. Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in psychology, Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in essay in politics, FPGA Design ASIC Verification.
Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for dissertation, functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and essay, e language. Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).
Worked on essay Mentor Graphics Schematic Entry Tool – Design Architect. Essay In Politics! Worked on PCI 32 bit @33Mhz Worked with Specman, an homework geometry proofs, ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture.
Familiar with 8085 Assembly Language. Essay! Familiar with software languages C and Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for one of the on employment modules in the chip.
Developed the test bench for the module. Wrote test cases in Verilog. Developed the different interfaces around the module. This network processor is designed to provide solution for in politics, 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of ocr terminal paper Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.
Designed and Synthesized SWATH cycle Controller module. Essay! RTL coding done in paper ideas, Verilog with Verilog-XL and Synthesized using Synplify Developed the essay in politics different interfaces around the Link 2 FPGA. Developed test plan for the functional verification and psychology paper ideas, wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the input side and takes the essay processed data to and from ocr terminal paper SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the essay input FPGA and SWATH FPGA. On Employment! This module does interface controlling from the in politics input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA.
This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level. Wrote test cases in 'e' language and ocr terminal, verified them using Modelsim simulator. Essay In Politics! Reported several bugs in the design and worked with the dissertation on educational designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the essay Emulation controller. The key features of the trace system ASIC are:
Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. Worksheet Statement! On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to essay, store channel data. trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into ocr terminal Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for essay, test cases. Engineering Design Center , Bangalore, INDIA.
Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for signal Processing. Designed the Hardware . Designed the FPGA CPLD . Done the functional simulation synthesis. Done extensive timing simulation with back annotating the dissertation sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to in politics, the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to statement, memory.
FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the in politics back end. Here we place and worksheet on writing a thesis statement, route the design and generate timing simulation data. From there one sdf(standard delay format) file is generated.
This includes all the internal delays of the device. Essay! The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the developmental psychology paper ideas test bench for timing simulation. So when timing simulation comes we load our design file and the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is essay, being configured from the system side, it cannot be a permanent data as from EPROM. On Margaret Sanger! So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at essay ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART.
Developed the architecture Designed and done RTL coding in on employment, VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and map the design to essay in politics, a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and ocr terminal paper, Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for essay in politics, being the developmental paper ideas best project team for the quarter of the essay in politics year 2000 for the Rrishti-1 Project. Worksheet Statement! Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to the verification of in politics Rrishti-1. Doing part-time courses in on margaret, San Jose University for.
Course 1- Advanced Logic Design (Winter 2001) Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on essay request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and psychology, my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to essay in politics, VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.
Languages: C, C++, perl, Unix Internals like Shell and Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Essays On Margaret! Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.
Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Essay! Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and statement, System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. Essay! The expected Value is checked with the RTL value to essay, verify the functionality of each block. Essay In Politics! Wrote high level monitors and stimulus models to homework geometry proofs, automate the verification process. In Politics! Analyzed the timing for ocr terminal paper, Data Windows using Logic Analyzer thus reducing the essay time for Data Window writes from 1.5 hrs to 18 mins for 1GB of dissertation on educational leadership memory on Hardware Emulation Platform.
Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in essay in politics, estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for conceiving, designing, developing and essay on employment, testing digital circuits for both ASIC and FPGA. Designed and essay in politics, tested the digital portion of the chip for television. Responsible for complete cycle from help proofs specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA. Essay In Politics! Developed simulations with VHDL and simulated it in Modelsim generating the statement test vectors for testing the FPGA. Developed Verilog testbenches and essay in politics, tested the circuit back annotating with SDF.
Checked the timing of the design generating test vectors for testing the ASIC. Designed and dissertation on educational leadership, tested Inter-Inter Connect (I2C) circuitry in essay, VHDL and on margaret sanger, Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. In Politics! Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.
Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and tested the read channel chip. Essays On Margaret Sanger! Worked on essay three different versions of the read channel. Designed the FPGA using Visual HDL generating the RTL for the design. Leadership! Tested the design writing VHDL test benches for the proper operation Placed and essay, routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.
Evaluated the design to test the psychology ideas read channel chip with various FPGA place and route tools. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and essay in politics, tested the Test Access Port (TAP) controller using Visual HDL. A Thesis Statement! Designed an IEEE standard TAP controller. Generated VHDL code from Visual HDL and in politics, tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Sanger! Developed Perl script for conversion of Spice netlist in to VERILOG netlist. The script written in essay in politics, perl takes in a Spice netlist and gives the Verilog netlist. On Employment! Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for in politics, this verilog file for checking the operation of the statement chip.
Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and essay in politics, other modules were coded and tested. Dissertation! Other Projects Design of essay in politics a Linear Interpolation Filter using Verilog and full custom IC layout. Design of a Simple Educational Processor using VHDL.
Designed and ocr terminal paper, simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of essay Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in help, documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills.
Strong Points include quicker grasp to new concepts, the ability to pursue matters in essay, great detail and able to developmental psychology ideas, work in a team. Bachelor of in politics Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for sanger, networking purpose on networking boards, which sends and in politics, receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for homework proofs, communication with Verilog.
Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to essay in politics, design, developed the essays on margaret sanger data networking boards and test benches for verification purpose of pre written functions in verilog . Simulation and in politics, hardware development of communication subsystems using the sections reconfigurable-prototyping.
Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Performed the developmental ideas design, capture the schematics and essay in politics, oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Client: FDD Container (UK)
The purpose of the project was to design and develop micro controller chip 80188EB for on writing a thesis, controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on essay higher priority algorithm, the homework signals of essay in politics higher priority is served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. Dissertation! Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks.
Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for essay in politics, controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the ocr terminal paper steam temperature. In Politics! Which receives the signals from Boiler sensors. If due to dissertation leadership, any reason the in politics temperature goes below specified level the paper alarm will be activated. Essay! It had the provision of printing the ocr terminal Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Essay! Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip. Programmed SRAM DRAM. Wrote verification code in ocr terminal, verilog C Performed the design, capture the in politics schematics and oversee the board layout.
Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for worksheet a thesis, calculating the Quantities of essay material required and its Costing, providing an easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of modifying as per the user specifications and standards.
It takes the Complete Details of a building (to be constructed) by providing an Interface and geometry, Calculates the in politics quantity of material required with its estimated cost, as per on writing a thesis, the standards specified. It provides an easy access for modifications. Environment: C, UNIX and essay, MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to geometry proofs, be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to essay in politics, get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for worksheet on writing a thesis, Updating the essay in politics Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of paper which the Core Part is essay in politics, handled using C++, and the GUI (Graphical User Interface) is developmental psychology paper ideas, handled using Visual C++ for Microsoft Windows 95 and essay, Microsoft Windows NT.
Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of leadership Locking Windows95 from being Loaded Unauthorized at the Boot time. Essay! Provides an paper ideas, Easy and essay in politics, Quick File Search. Provides Quick Access to on educational leadership, file Opening and Executing.
Provides File Viewing facility before editing the files, giving an Easy access to in politics, Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and essays, MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Essay! Was a member of the team, which designed the dissertation system? Other responsibilities included coding and in politics, testing. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B.
References: Available on request. Nine and a half years of ocr terminal strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and essay, setting up Verification environment in Verilog/VHDL. Good knowledge of essay on employment PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to in politics, local) PCI 9656. Wrote random tests for essay, the verification of the PCI 9656 for Direct Slave . Essay! Direct Slave means that the essay chip is the in politics slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite.
Worked on FIFO testing. There were 2 FIFOs. One for worksheet a thesis statement, the Direct slave read and the other for the direct slave write. Essay In Politics! Wrote various test and verified the functionality of the dissertation on educational leadership FIFOs for both the empty and full condition. There were numerous condition to essay, fill and empty the FIFO. One such condition could be no grant on help geometry the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . These modes are the local bus types.
M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is in politics, 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for essay on employment, the Seamless CVE (Co- Verification Environment).
The Hardware and Software Co- Verification helped in essay, software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. On Writing Statement! Satisfied the customer about the essay utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of on writing a thesis competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of essay in politics a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of developmental classification of the packet. In Politics! The packets could be classified on the basis of the header or any byte of the data payload.
The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and essays on margaret, non zbt modes. In Politics! The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Developmental Psychology Paper! Wrote diagnostics to verify the system bus interface using Verilog.
Build the essay in politics Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for ocr terminal, Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and essay, Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC.
Translated the unit level test cases for essay on employment, HDLC to system level tests. In Politics! Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface.
Verified the above functionality of the NOC by writing the functional models in Verilog. Ocr Terminal! Verified functional models. Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and in politics, dequeuing of the packet through the star address in PB and the skip over dissertation leadership mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in in politics, the TDM manner. Functional model of the essays on margaret sanger NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the essay test bench and on writing, wrote task for in politics, specific functionality. Developed test plans, test cases for the Chip Level Verification of the paper ASIC using Verilog. Found and fixed bugs.
Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of HDLC Controller (Project Lead) Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and in politics, checker were implemented. Leadership! The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC.
Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96.
Development of Test Bench for essay, BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.
November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and ocr terminal paper, keys were scanned. Whenever any key was pressed, the make and in politics, the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the on writing statement standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout.
VLSI Logic design - Complete design flow from RTL to layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Essay! Complete understanding in on educational leadership, architectures of PCI OHCI. Proficient with USB. Knowledge in Unix, Perl and 'C'.
Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Essay! Expertise in Altera /APEX FPGA. Experience in paper, Assembly Language. Essay! Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. Essays On Margaret Sanger! P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices.
Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99.
Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. The Total No. of gates is 1.2 Millions.
It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is essay in politics, Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by help providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for in politics, the system vendor to provide differentiated value addition to the system. It is on margaret sanger, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.
The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for essay, the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA. On Educational Leadership! Developed the verification methods created testcases both normal corner for UART, SPI DMA.
Did the RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for essay in politics, waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the essay on employment UMAC in VERILOG. This s going to essay, be used and cable modem chip. The design was target for sanger, APEX FPGA from in politics altera 20K200.
The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from paper simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module. The design operates in 3 different frequencies.
The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is essay, working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for P R. Synthesis by worksheet a thesis Syniplify from essay synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for sanger, IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.
Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to essay, the microprocessor. The microprocessor reads the on educational leadership data from dpram which was written by the ATM fpga.
Designed the code in essay in politics, Verilog. Compiled and simulated in dissertation leadership, MTI Verilog simulator (Model Tech). Essay! Renoir Tool and Xilinx Foundation series 2.1I from essay Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated.
The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into in politics the memory for burst of transaction. Developed Designed the logic in verilog which is specific to Disk Module and it provides the following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS.
In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is paper, 64 bytes. There are two downstream FIFOs and two upstream FIFOs. In Politics! The FIFOs are used in on writing, ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is in politics, supported. Synthesized the essay on employment OC3_FPGA, which had the modules like Lucent PCI Master and Target. Essay! Module ware Utopia Master and Slave. Interface Data Path Between Tetra and dissertation leadership, SAR. Completed Place and essay, Route of the paper above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU.
Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of essay Open Host Controller, which controls the transaction running on USB bus. It fetches the worksheet on writing Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI.
Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is interfaced to the PCI bus for accessing the system memory. Designed this core using both VHDL and VERILOG. This design has different types of essay modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function.
Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and essays on margaret, Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the essay ED/TD's or data's for USB devices from main memory or updating the data from homework geometry proofs USB devices to main memory. PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Synthesized the essay logic using Exemplar's Leonardo tool.
Max+plus II tool is a thesis statement, used for Place and essay in politics, Route. Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into paper ideas the Altera Flex10k100A device. Essay! Mapping the whole design into worksheet a thesis statement ASIC Library and testing is in in politics, progress. Total gate count for OHCI project is 33,000 gates. Project : Design and verification of Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to paper, the computer through USB. It consists of essay in politics video camera interface, scalar, a high quality compressor and USB interface.
The picture information coming from the statement camera is essay, processed by the hearsee block. This data is first scaled down by scalar block according to the mode of operation. This scaled down data is psychology ideas, compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of essay a USB Device Core. Project : Design of FIFO.
Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and paper ideas, Stepper Motor Controller. Used the in politics add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of geometry proofs Engineering (Electronics and Communication) 1997.
Madras University, INDIA. Essay In Politics! 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols. Ocr Terminal! Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of essay full chip and block level designs.
Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for on educational, physical verification, TransEDA and essay, HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and ocr terminal, WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at essay the networking applications. Responsibilities require me to write directed tests to verify the psychology paper ideas tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the test vectors from the viewpoint of in politics code coverage, and furnish suggestions to the verification team as per help proofs, the findings.
Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. Essay In Politics! fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is essay, used in automobiles for communicating between various controllers inside the vehicle.
The project involved converting the essay in politics latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to convert the RTL to flip-flop based design and simulate the essay design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on essay in politics Motorola's Mcore processors. Ideas! Responsibilities required me to verify, Synthesize and PR the essay Timer block. This project involved the full Network design cycle, except for RTL Coding.
MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. Paper! The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation.
Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of essay in politics 8-bit Microcontrollers(SPC700 series) for ocr terminal paper, Sony Corp(04/98 - 02/99) SPC700 series is essay, a general-purpose programmable 8-bit microcontrollers originally designed by SONY. Essays! The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Essay In Politics! Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip.
Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the essays stimulus file from ANDO-DIC 8031/32 format to in politics, a Verilog compatible format. This saved a lot of paper expense to the company. Granada Consultancy Services. Assistant System Analyst.
American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for in politics, American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Each IG was responsible for worksheet on writing a thesis, modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader.
Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Graphical User Interface. Essay In Politics! It also consisted training on Software Development Methodologies. It also involved a project in homework help geometry, C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.
Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in essay, Computer-Aided Design Center, China. Essay On Employment! MSCE in Computer Engineering, WU, China.
BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in in politics, all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for MPU-based embedded application systems. Dissertation On Educational! In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in firmware programming in in politics, C/C++ under PC DOS, VxWorks and QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
Excited by ocr terminal paper the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and China in the positions of essay in politics Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over psychology paper ideas 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and essay in politics, Control system. Following are my some ASIC/FPGA hardware and developmental paper, system design experience in real world in order: Vegatron Networks, Toronto, Canada.
2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for essay, the 4-million gates ASIC based on dissertation on educational multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.
May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. Essay In Politics! RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.
Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. On Employment! Partitioned core-based design and Coded in Verilog at RTL.
Designed core-based PCI application interface and wrote testbench for it. Essay! Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores. Synthesized with Tcl scripts , and paper, analyzed timing to fix timing issues at RTL and Gate level. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and in politics, back-annotated. Defined software interface and supported firmware designers to write ASIC driver.
Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for ocr terminal paper, MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz.
Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Developed and implemented the dynamical linecard, modem bandwidth allocation and essay, sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Implemented traffic congestion control based on modem and geometry, subport backpressure signals. Wrote the in politics new version of the ASIC/FPGA design specification, verification and test plan. Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions. Wrote model driver and testbench in Verilog and Vera to simulate each new block and ocr terminal, top level.
Synthesized the ASIC by DC, FPGA by Synplify with constraints and essay, Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Wrote test script for VxWorks dshell and VisionICE to help geometry, test traffic in lab by essay in politics Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for psychology, a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in essay in politics, real world in cooperation of EE and worksheet a thesis statement, CS departments.
Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and essay in politics, architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in developmental psychology paper, VHDL at RTL. Essay! Designed an EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime. Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board.
VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and leadership, Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench. Essay! CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA.
Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for homework geometry proofs, a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in essay, C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for essays sanger, a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in Xilinx F1.5, and board schematic and essay in politics, PCB design in developmental ideas, OrCAD. Essay In Politics! PC DOS programming and MCU 8051 firmware programming in C.
Digital Design Center, Wuhan, China. 1994 Sept - 1996 June. Ph.D. Project. Dissertation Leadership! Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Essay In Politics! Developing fast and precise online algorithms based on microscope and CCD sensors.
Developed a MCU-base prototyping board to demo a new fast and developmental ideas, precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for customers.
Leaded a team to in politics, successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in C and debugged in labs. Paper Ideas! Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.
Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and essay in politics, PCB design in essays sanger, Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C. Developing an essay, electronic system to be used for teaching spoken English. Leaded a team to design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to control an essay, audio network comprised of all 64 audio terminals. In Politics! Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.
Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.
Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in essay on employment, C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. In Politics! Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design. Primetime Training Workshop PowerPC 8260 Workshop.
Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and essay, Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.